An electronic module has a sealing part 90; electronic elements 15, 25 provided in the sealing part 90; back-surface exposed conductors 10, 20, 30 having back-surface exposed parts 12, 22, 32, which have back surfaces exposed from the sealing part 90, and having one-terminal parts 11, 21, 31, which extend from the back-surface exposed parts 12, 22, 32 and protrude outward from a side of the sealing part 90; and back-surface unexposed conductors 40, 50 having unexposed parts 42, 52, which are sealed in the sealing part 90, and having other-terminal parts 41, 51, which extend from the unexposed parts 42, 52 and protrude outward from a side of the sealing part 90. The electronic elements 15, 25 are placed on the back-surface exposed parts 12, 22, 32. The other-terminal parts 41, 51 have a width narrower than a width of the one-terminal parts 11, 21, 31.

A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.

A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.

The present invention provides a leadframe component and a package structure. The leadframe component includes a first leadframe and a second leadframe. The first leadframe includes a first chip-mounting portion for carrying a first chip, a first coil portion, a plurality of first pins and a plurality of first floated pins. The second leadframe includes a second chip-mounting portion for carrying a second chip, a second coil portion, a plurality of second pins and a plurality of second floated pins. The first leadframe is disposed above or under the second leadframe for aligning the first coil portion with the second coil portion.

The instant disclosure provides a method for manufacturing a package structure of a folding magnetic coupling isolator. The method includes providing a leadframe structure including a frame body and a first and a second leadframes connected to the frame body, the first and second leadframes including first and second chip-mounting portions, first and second coil portions, and a plurality of first and second pins and floated pins; disposing the first and second chips on the first and second chip-mounting portions and establishing electrical connections between the first and second chips and the first and second pins; and rotating the first leadframe relative to the frame body and moving the first leadframe to a position above or under the second leadframe, thereby electrically isolating the first leadframe from the second leadframe. The first coil portion and the second coil portion are aligned with and magnetically coupled to each other.

There is provided a novel Cu bonding wire that achieves a favorable FAB shape and achieve a favorable bond reliability of the 2nd bonding part even in a rigorous high-temperature environment. The bonding wire for semiconductor devices includes a core material of Cu or Cu alloy, and a coating layer having a total concentration of Pd and Ni of 90 atomic % or more formed on a surface of the core material. The bonding wire is characterized in that: in a concentration profile in a depth direction of the wire obtained by performing measurement using Auger electron spectroscopy (AES) so that the number of measurement points in the depth direction is 50 or more for the coating layer, a thickness of the coating layer is 10 nm or more and 130 nm or less, an average value X is 0.2 or more and 35.0 or less where X is defined as an average value of a ratio of a Pd concentration C.sub.Pd (atomic %) to an Ni concentration C.sub.Ni (atomic %), C.sub.Pd/C.sub.Ni, for all measurement points in the coating layer, the total number of measurement points in the coating layer whose absolute deviation from the average value X is 0.3X or less is 50% or more relative to the total number of measurement points in the coating layer, and the bonding wire satisfies at least one of following conditions (i) and (ii): (i) a concentration of In relative to the entire wire is 1 ppm by mass or more and 100 ppm by mass or less; and (ii) a concentration of Ag relative to the entire wire is 1 ppm by mass or more and 500 ppm by mass or less.

A method of producing a semiconductor package includes providing a molded plate that is formed of a first mold compound, providing a lead frame assembly that includes a lead frame and a semiconductor die mounted on a die pad of the lead frame, arranging the lead frame assembly and the molded plate within a molding chamber of a molding tool such that the molded plate is interposed between the die pad and an interior surface of the molding chamber, and performing a molding process that fills the molding chamber with a second mold compound that encapsulates the semiconductor die.

A semiconductor package includes a first structure that includes an upper connection pattern; a second structure that includes a lower connection pattern; and a connection structure that connects the upper connection pattern of the first structure to the lower connection pattern of the second structure, wherein the connection structure includes a lower conductor connected to the upper connection pattern of the first structure; an upper conductor connected to the lower conductor and the lower connection pattern of the second structure; and a dielectric pattern that at least partially surrounds the upper conductor, and the dielectric pattern includes a first surface in contact with the upper conductor; and a second surface in contact with the lower conductor.

An integrated circuit (IC) package includes an interconnect. The interconnect has a connecting tie bar and a die pad. The IC package also includes a die mounted on the die pad of the interconnect. The IC package further includes a wire bond coupled to the die and the connecting tie bar to provide a current path between the die and the connecting tie bar.

A semiconductor device includes a pad formed on a surface of a substrate, a bonding wire for connecting the pad to an external circuit, and a resin layer covering at least a connection portion between the pad and the bonding wire and exposing at least a part of the substrate outside the pad.