An object is to provide a technique capable of improving the power efficiency of a semiconductor device. The semiconductor device includes first to sixth parallel connection bodies, each including a semiconductor switching element and a diode connected in antiparallel to the semiconductor switching element. At least one of the voltage drops of the second parallel connection body and the third parallel connection body is smaller than a voltage drop of at least one of the first parallel connection body, the fourth parallel connection body, the fifth parallel connection body, and the sixth parallel connection body.

A semiconductor device includes a semiconductor element and a first connection member. The semiconductor element includes a substrate and an electrode pad. The substrate includes a transistor formation region, in which a transistor is formed and which is shaped to be non-quadrangular. The electrode pad is located on the transistor formation region. The first connection member is connected to the electrode pad at one location. The electrode pad is arranged to cover a center of gravity of the transistor formation region in a plan view of the electrode pad. In the plan view, a connection region in which the first connection member is connected to the electrode pad includes a center of gravity position of the transistor formation region.

A semiconductor device includes a semiconductor chip having a main electrode on a front surface thereof, a wiring board having a front surface to which a rear surface of the semiconductor chip is bonded, a sealing member sealing the wiring board and the semiconductor chip, and an adhesive layer including at least two adhesive films that are laminated to each other. The adhesive layer is provided on surfaces of the wiring board and the semiconductor chip so that the sealing member seals the wiring board and the semiconductor chip via the adhesive layer. As a result, the sealing member is able to reliably seal the semiconductor chip and wiring board via the adhesive layer, thereby preventing an occurrence and extension of separation.

An object is to provide a semiconductor device which suppresses poor bonding between a metal pattern and an electrode terminal due to insufficient temperature rise at the time of bonding the metal pattern and the electrode terminal. The electrode terminal is branched into a plurality of branch portions in a width direction on one end side of an extending direction thereof, of the plurality of branch portions, a first branch portion and a second branch portion are bonded on the metal pattern via a bonding material, respectively, the first branch portion has a wider width than that of the second branch portion, and the bonding material between the second branch portion and the metal pattern is thinner than the bonding material between the first branch portion and the metal pattern.

A semiconductor module includes a substrate, a semiconductor chip arranged on the substrate, and a first connecting element for electrically connecting the semiconductor chip to a conductor track and/or to a further component of the semiconductor module. At least part of the first connecting element lies in surface contact with the semiconductor chip and the substrate and also the conductor track and/or the further component. The semiconductor module includes a second connecting element for electrically connecting the semiconductor chip to the conductor track and/or to the further component. The second connecting element is configured in the form of a wire or a strip,

A semiconductor device includes a semiconductor element having an NiV electrode and a conductor, the semiconductor element and the conductor being bonded via Sn-based lead-free solder. In the semiconductor device, an SnV compound layer and an (Ni, Cu)3Sn4 compound layer adjacent to the SnV compound are formed adjacent to an interface between the semiconductor element and the Sn-based lead-free solder. A manufacturing method for a semiconductor device according to the present invention includes: causing the Sn-based lead-free solder and the NiV electrode to react with each other to form an SnV layer and an (Ni, Cu)3Sn4 compound layer; and following formation of the SnV layer, leaving an unreacted layer of the NiV electrode, the unreacted layer having not reacted with the Sn-based lead-free solder, intact.

An electronic device includes a package structure, a conductive terminal exposed outside the package structure, a semiconductor die in the package structure, and a bond wire having contiguous first and second portions. The first portion has a first end and a second end, the first end connected to the semiconductor die by a first bond and the second end connected to the conductive terminal by a second bond. The second portion has a first end and a second end, the first end of the second portion connected to the second end of the first portion, and the second end of the second portion connected to the conductive terminal by a third bond.

A wire bonding apparatus connecting a lead of a mounted member with an electrode of a semiconductor die through a wire comprises a capillary through which the wire is inserted, a shape acquisition part which acquires the shape of the lead to which the wire is connected, a calculating part which calculates an extending direction of a wire tail extending from the end of the capillary based on the shape of a lead to which the wire is connected next, and a cutting part which moves the capillary in the extending direction and cuts the wire to form the wire tail after the lead is connected with the electrode through the wire. Thus, in the wire bonding using wedge bonding, joining part tails (183a, 283a, 383a) formed in continuation to a first bonding point can be prevented from coming into contact with each other.

The invention relates to a power electronic switching device having a substrate, which has a non-conductive insulation layer on which at least one first conductor track 40 and at least one second conductor track 50 are applied. The first conductor track 40 is assigned an electrical DC voltage potential DC+ of the power electronic switching device and the one second conductor track 50 is assigned an electrical AC voltage potential AC of the power electronic switching device. At three first partial power switches are arranged on the first conductor track. At least three second partial power switches are arranged on the second conductor track. The at least three first partial power switches are connected electrically in parallel with each other to form a first parallel circuit and the at least three second partial power switches are electrically connected in parallel with each other to form a second parallel circuit. The at least three first partial power switches and the at least three second partial power switches are arranged on the substrate 30 in a chessboard-like pattern.

In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.