Patent classifications
H01L2224/4846
Packages with electrical fuses
In examples, a package comprises a semiconductor die having a device side and a bond pad on the device side, a conductive terminal exposed to an exterior of the package, and an electrical fuse. The electrical fuse comprises a conductive ball coupled to the bond pad, and a bond wire coupled to the conductive terminal. The bond wire is stitch-bonded to the conductive ball.
SEMICONDUCTOR DEVICE
A semiconductor device with front and back surfaces, and a side surface having first and second sides opposite to each other, and third and fourth sides opposite to each other. The semiconductor device includes a plurality of circuit boards surrounded by the first to fourth sides, the circuit boards each including an insulating board and a conductive plate, a first lead frame including a first terminal portion extending upward and being bent toward the first side, a second lead frame including a second terminal portion extending upward and being bent toward the second side, and a resin-filled portion provided in a first gap between the first terminal portion and the second terminal portion, the resin-filled portion having a concave portion recessed in a direction from the front surface toward the back surface so that an insulating insertion member is inserted into the concave portion.
Power module with metal substrate
A power semiconductor module includes a substrate of planar sheet metal including a plurality of islands that are each defined by channels that extend between upper and lower surfaces of the substrate, a first semiconductor die mounted on a first one of the islands, a molded body of encapsulant that covers the metal substrate, fills the channels, and encapsulates the first semiconductor die, a hole in the molded body that extends to a recess in the upper surface of the substrate, and a press-fit connector arranged in the hole such an interior end of the press-fit connector is mechanically and electrically connected to the substrate.
SEMICONDUCTOR DEVICES HAVING WIRE BONDING STRUCTURES AND METHODS OF FABRICATING THE SAME
A semiconductor device includes a first device having a first pad; a second device having a second pad; and a bonding wire electrically connecting the first device and the second device to each other via the first pad and the second pad. The bonding wire includes: a first bonding structure provided at a first end of the bonding wire, electrically connected to the first device and includes: a first ball bonding region; and a first stitch bonding region; and a second bonding structure provided at a second end opposite of the first end of the bonding wire and electrically connected to the second device.
Cooler with emi-limiting inductor
A power device package includes a dielectric substrate having an upper conductor layer and a lower conductor layer, a semiconductor die coupled to the upper conductor layer of the dielectric substrate via conductive adhesive, a cooler including a protruding hillock having a top surface and outer sides, the lower conductor layer of the dielectric substrate being coupled to the surface of the protruding hillock via an adhesive, and a magnetic material attached mateably around the protruding hillock. The magnetic material includes inner sides abutting the outer sides of the protruding hillock.
Semiconductor device
An object of the present invention is to shorten the switching delay time of a semiconductor device. Transistor units are provided between a source bus line and a drain bus line that are provided apart from each other in a first direction, and a plurality of gate electrodes that extends in the first direction and is provided apart from each other in a second direction orthogonal to the first direction is provided in the transistor units. One ends of the gate electrodes on the source bus line side are coupled by a gate connection line extending in the second direction, and a gate bus line electrically coupled to the gate connection line is provided above the gate connection line. The gate electrodes and the gate connection line are formed using a wiring layer of the first layer, the source bus line and the drain bus line are formed using a wiring layer of the second layer, and the gate bus line is formed using a wiring layer of the third layer.
Molded package with chip carrier comprising brazed electrically conductive layers
A method of manufacturing a package, wherein the method comprises a forming a chip carrier by covering a thermally conductive and electrically insulating core on both opposing main surfaces thereof at least partially by a respective electrically conductive layer by brazing the respective electrically conductive layer on a respective one of the main surfaces; a mounting at least one electronic chip on the chip carrier; an electrically coupling an electrically conductive contact structure with the at least one electronic chip; and an encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip by a mold-type encapsulant.
Semiconductor device
A semiconductor device includes a plurality of semiconductor elements; insulating circuit boards each including an insulating substrate, a circuit portion on a front surface of the insulating substrate connected to one semiconductor element, and a metal portion on a rear surface of the insulating substrate; a metal plate joined to the metal portions of the plurality of insulating circuit boards; and a joint member joining the plurality of insulating circuit boards to the metal plate. The metal plate has a front surface in which the insulating circuit boards are arranged apart from each other, and a rear surface including first regions corresponding to positions of the metal portions and second regions other than the first regions. At least a part of a surface of each of the first regions has a surface work-hardened layer, and the second regions have a hardness different from that of the surface work-hardened layer.
Semiconductor module
A semiconductor module, comprises a substrate plate; a semiconductor switch chip and a diode chip attached to a collector conductor on the substrate plate, wherein the diode chip is electrically connected antiparallel to the semiconductor switch chip; wherein the semiconductor switch chip is electrically connected via bond wires to an emitter conductor on the substrate plate providing a first emitter current path, which emitter conductor is arranged oppositely to the semiconductor switch chip with respect to the diode chip; wherein a gate electrode of the semiconductor switch chip is electrically connected via a bond wire to a gate conductor on the substrate plate providing a gate current path, which gate conductor is arranged oppositely to the semiconductor switch chip with respect to the diode chip; and wherein a protruding area of the emitter conductor runs besides the diode chip towards the first semiconductor switch chip and the first semiconductor switch chip is directly connected via a bond wire with the protruding area providing an additional emitter current path running at least partially along the gate current path. The semiconductor switch chip is a first semiconductor switch chip and the diode chip is a first diode chip, which are arranged in a first row. The semiconductor module comprises further a second row of a second semiconductor switch chip and a second diode chip attached to the collector conductor, wherein the diode chip of each row is electrically connected antiparallel to the semiconductor switch chip of the same row and the first and second rows are electrically connected in parallel. The first semiconductor switch chip is arranged besides the second diode chip and the second semiconductor chip is arranged besides the first diode chip.
Method of manufacturing a semiconductor power package
A method of manufacturing a semiconductor power package includes: providing a pre-molded chip housing and an electrically conducting chip carrier cast-in-place in the pre-molded chip housing; bonding a power semiconductor chip on the electrically conducting chip carrier; and applying a covering material so as to embed the power semiconductor chip. The covering material has an elastic modulus less than an elastic modulus of a material of the pre-molded chip housing and/or a thermal conductivity greater than a thermal conductivity of the material of the pre-molded chip housing and/or a temperature stability greater than a temperature stability of the pre-molded chip housing.