The present invention relates to a power semiconductor module including a first heat dissipation substrate, a semiconductor chip, a lead plate, a PCB, and a heat dissipation plate that are packaged within a casing, wherein dualization of a heat dissipation structure is applied to facilitate superior heat dissipation performance compared to a conventional power semiconductor module.

A power semiconductor device includes: a power semiconductor element; a control circuit that controls the power semiconductor element; a control substrate having the control circuit mounted thereon; a lid arranged to overlap with at least a portion of the control substrate in a first direction; and at least one external connection terminal having a first portion connected with the control substrate, a second portion to be connected with an external apparatus, and a third portion located between the first portion and the second portion and fixed to the lid, the first portion being constituted as a press-fit portion.

A semiconductor device includes a first circuit, a second circuit, a wiring member, and a bonding material. The wiring member is connected to one of the first circuit and the second circuit. The bonding material is connected to the other of the first circuit and the second circuit. The wiring member includes a first end, a second end, and a top. The first end and the second end are connected to one of the first circuit and the second circuit. The top is located between the first end and the second end. The top is connected to the other of the first circuit and the second circuit with the bonding material in between.

The present disclosure has been conceived to solve such a problem, and it is an object of the present disclosure to provide a semiconductor device enabling reduction in cost. A semiconductor device according to the present disclosure includes: a base plate; an insulating substrate disposed over the base plate; a semiconductor chip disposed over the insulating substrate; a first resin case and a second resin case attached to the base plate to enclose the insulating substrate and the semiconductor chip, and fitted together; and a sealing material to seal the insulating substrate and the semiconductor chip, wherein the first resin case and the second resin case are formed of resin materials having different comparative tracking indices.

A wire bonding apparatus connecting a lead of a mounted member with an electrode of a semiconductor die through a wire comprises a capillary through which the wire is inserted, a shape acquisition part which acquires the shape of the lead to which the wire is connected, a calculating part which calculates an extending direction of a wire tail extending from the end of the capillary based on the shape of a lead to which the wire is connected next, and a cutting part which moves the capillary in the extending direction and cuts the wire to form the wire tail after the lead is connected with the electrode through the wire. Thus, in the wire bonding using wedge bonding, joining part tails (183a, 283a, 383a) formed in continuation to a first bonding point can be prevented from coming into contact with each other.

Provided is a semiconductor apparatus comprising: a semiconductor substrate; an element electrode provided above the semiconductor substrate; an element electrode pad electrically connected to the element electrode; and a wire configured to connect to the element electrode pad at a plurality of connection points, wherein the semiconductor substrate includes an emitter region of a first conductivity type arrayed in an array direction, the emitter region facing the element electrode on an upper surface of the semiconductor substrate, wherein a density of the emitter region below a connection point of any of the wires is different from a density of the emitter region below a connection point of any other of the wires.

A semiconductor package may include: a base layer; first to Nth semiconductor chips (N is a natural number of 2 or more) sequentially offset stacked over the base layer so that a chip pad portion of one side edge region is exposed, wherein the chip pad portion includes a chip pad and includes a redistribution pad that partially contacts the chip pad and extends away from the chip pad; and a bonding wire connecting the chip pad of a kth semiconductor chip among the first to Nth semiconductor chips to the redistribution pad of a k−1th semiconductor chip or a k+1th semiconductor chip when k is a natural number greater than 1 and the bonding wire connecting the chip pad of the kth semiconductor chip to a pad of the base layer or the redistribution pad of the k+1th semiconductor chip when k is 1.

Power module has press-fit pins for the electrical and mechanical connection for the terminals, insertable into sleeves on the substrate. The substrate rests on a baseplate. Potential alignment frame ensures the accuracy of all elements. The mechanical and electrical connection of the power and signal terminals is realized by multiple (high-current) or single press-fit connections. When inserting the pins, they are fitting tightly in these sleeves by overcoming a frictional force and after fitting is established, for each single pin-fit, an electrical contact over a surface is established.

A method for fabricating a hermetic electronic package includes providing a package body; hermetically coupling a package base plate to the package body; thermally coupling a substrate to the base plate; thermally mounting a semiconductor device to the substrate; bonding at least one high-current input/output (I/O) terminal to the first metalized region of the substrate by a strap terminal that is an integral high current heatsink terminal. A ceramic seal surrounding the at least one high-current I/O terminal is hermetically bonded to an outer surface of the package body. A metal hermetic seal washer surrounding the at least one high-current I/O terminal is hermetically bonded to the ceramic seal and to a portion of the at least one high-current I/O terminal. A lid is seam welded onto the package body.

A semiconductor arrangement includes at least two switching devices of a first type electrically coupled in parallel between a first terminal and a second terminal, and at least two switching devices of a second type electrically coupled in parallel between the second terminal and a third terminal. The switching devices of the first type and the switching devices of the second type are arranged in a power semiconductor module that has first and second longitudinal sides and first and second narrow sides. The switching devices of the first type and the switching devices of the second type are arranged next to each other in at least one row extending in a first horizontal direction that is parallel to the first and second longitudinal sides, such that within each of the at least one rows no more than two switching devices of the same type are arranged in direct succession.