A single chip power diode includes a semiconductor body having an anode region coupled to a first load terminal and a cathode region coupled to a second load terminal. An edge termination region surrounding an active region is terminated by a chip edge. The semiconductor body thickness is defined by a distance between at least one first interface area formed between the first load terminal and the anode region and a second interface area formed between the second load terminal and the cathode region. At least one inactive subregion is included in the active region. Each inactive subregion: has a blocking area with a minimal lateral extension of at least 20% of a drift region thickness; configured to prevent crossing of the load current between the first load terminal and the semiconductor body through the blocking area; and at least partially not arranged adjacent to the edge termination region.

A semiconductor device includes a semiconductor element, a substrate including an insulating board, and first conductive plate and second conductive plate on the insulating board, and a wiring unit including a first lead frame electrically connected to the first conductive plate and having a first wiring portion wired parallel to the insulating board, a second lead frame electrically connected to the second conductive plate, and having a second wiring portion above the first lead frame and overlapping the first wiring portion in a plan view at a superimposed area, a gap between the first and second lead frames being formed in the superimposed area, and a wiring holding portion holding the first and second lead frames. The wiring holding portion includes a wiring gap portion which fills in the gap, and a wiring surface portion disposed over the second wiring portion in the superimposed area.

A lead frame is provided with a die pad portion, a first lead portion, a second lead portion, and an extension portion extending from a corner portion neighborhood of the die pad portion to the outside of the die pad portion. The first lead portion has a first terminal portion and a first lead post portion positioned on a side closer to the die pad portion relative to the first terminal portion and electrically connected to the first terminal portion. The second lead portion has a second terminal portion, a third terminal portion positioned between the first terminal portion and the second terminal portion, and a second lead post portion positioned on a side closer to the die pad portion relative to the second terminal portion and the third terminal portion and electrically connected to the second terminal portion and the third terminal portion.

A bonding wire for connecting a first pad to a second pad is provided. The bonding wire includes a ball part bonded to the first pad, a neck part formed on the ball part, and a wire part extending from the neck part to the second pad. Less than an entire portion of a top surface of the neck part is covered by the wire part, and the wire part is in contact with the neck part, the ball part, and the first pad.

The semiconductor device includes a substrate having a main surface, a plurality of conductive patterns provided on the main surface, a plurality of switching elements disposed on one of the conductive patterns, each switching element having a first electrode and a second electrode and being connected to the one of the conductive patterns through its first or second electrode, and at least one first wiring member each directly connecting the first electrodes of two switching elements that are respectively disposed on different conductive patterns and are electrically connected in parallel.

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, amounting layer, switching elements, a moisture-resistant layer and a sealing resin. The substrate has a front surface facing in a thickness direction. The mounting layer is electrically conductive and disposed on the front surface. Each switching element includes an element front surface facing in the same direction in which the front surface faces along the thickness direction, a back surface facing in the opposite direction of the element front surface, and a side surface connected to the element front surface and the back surface. The switching elements are electrically bonded to the mounting layer with their back surfaces facing the front surface. The moisture-resistant layer covers at least one side surface. The sealing resin covers the switching elements and the moisture-resistant layer. The moisture-resistant layer is held in contact with the mounting layer and the side surface so as to be spanned between the mounting layer and the side surface in the thickness direction.

A single chip power diode includes a semiconductor body having an anode region coupled to a first load terminal and a cathode region coupled to a second load terminal. An edge termination region surrounding an active region is terminated by a chip edge. The semiconductor body thickness is defined by a distance between at least one first interface area formed between the first load terminal and the anode region and a second interface area formed between the second load terminal and the cathode region. At least one inactive subregion is included in the active region. Each inactive subregion: has a blocking area with a minimal lateral extension of at least 20% of a drift region thickness; configured to prevent crossing of the load current between the first load terminal and the semiconductor body through the blocking area; and at least partially not arranged adjacent to the edge termination region.

A semiconductor device including a semiconductor unit that has a first arm part, which includes: first and second semiconductor chips having first and second control electrodes on their front surfaces, a first circuit pattern where the first and second semiconductor chips are disposed, a second circuit pattern to which the first and second control electrodes are connected, and a first control wire electrically connecting the first and second control electrodes and the second circuit pattern sequentially in a direction; and a second arm part, which includes third and fourth semiconductor chips having third and fourth control electrodes on their front surfaces, a third circuit pattern where the third and fourth semiconductor chips are disposed, a fourth circuit pattern to which the third and fourth control electrodes are connected, and a second control wire electrically connecting the third and fourth control electrodes and the fourth circuit pattern sequentially in the direction.

Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding first and second bond pad surfaces that face toward each other. First bond pads can be positioned at least proximate to the first bond pad surface and second bond pads can be positioned at least proximate to the second bond pad surface. A package connection site can provide electrical communication between the first microfeature device and components external to the package. A wirebond can be coupled between at least one of the first bond pads and the package connection site, and an electrically conductive link can be coupled between the first microfeature device and at least one of the second bond pads of the second microfeature device. Accordingly, the first microfeature device can form a portion of an electrical link to the second microfeature device.

A variety of footed and leadless semiconductor packages, with either exposed or isolated die pads, are described. Some of the packages have leads with highly coplanar feet that protrude from a plastic body, facilitating mounting the packages on printed circuit boards using wave-soldering techniques.