There is provided a solid state imaging apparatus, including: an optical film layer on which a solid state image sensor is mounted; a multifunctional chip laminated at a periphery of the solid state image sensor in the optical film layer being electrically contacted with the optical film layer via a metal body; a sealing resin layer for sealing the periphery where the multifunctional chip is laminated on the optical film layer; and a concave structure for blocking a flow of the sealing resin in a liquid state when the sealing resin layer is formed at the periphery of the sealing resin layer. Also, a method of producing the solid state imaging apparatus is also provided.

In accordance with an embodiment of the present invention, a semiconductor device includes a first bond pad disposed at a first side of a substrate. The first bond pad includes a first plurality of pad segments. At least one pad segment of the first plurality of pad segments is electrically isolated from the remaining pad segments of the first plurality of pad segments.

In accordance with an embodiment of the present invention, a semiconductor device includes a first bond pad disposed at a first side of a substrate. The first bond pad includes a first plurality of pad segments. At least one pad segment of the first plurality of pad segments is electrically isolated from the remaining pad segments of the first plurality of pad segments.

The method includes preparing a plurality of light-emitting units, one of the plurality of light-emitting units comprising an electrode, a light-emitting stack, and a protection layer with a first part covering the electrode and a second part which comprises a portion surrounding the electrode and covers the light-emitting stack; removing the portion without removing the first part; forming a wavelength conversion layer on the first part and the light-emitting stack not covered by the second part; and removing the first part to substantially expose the electrode.

An interconnect device and a method of forming the interconnect device are provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. One or more dielectric films are formed along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits, while using some of the pads as hard masks. The first opening and the second opening are filled with a conductive material to form a conductive plug.

An integrated circuit structure includes a first and a second semiconductor chip. The first semiconductor chip includes a first substrate and a first plurality of dielectric layers underlying the first substrate. The second semiconductor chip includes a second substrate and a second plurality of dielectric layers over the second substrate, wherein the first and the second plurality of dielectric layers are bonded to each other. A metal pad is in the second plurality of dielectric layers. A redistribution line is over the first substrate. A conductive plug is electrically coupled to the redistribution line. The conductive plug includes a first portion extending from a top surface of the first substrate to a bottom surface of the first substrate, and a second portion extending from the bottom surface of the first substrate to the metal pad. A bottom surface of the second portion contacts a top surface of the metal pad.

To arrange a protective material horizontally with respect to a substrate plane without the protective material coming into contact with wires in a wire-bonded semiconductor package. The semiconductor package includes a protective material, a substrate, bumps, and a semiconductor chip. The bumps are provided on a chip plane of the semiconductor chip and are connected to the substrate via wires. The semiconductor chip is laminated on the substrate. A support is provided on the chip plane to support the protective material at a position where the height from the chip plane of the semiconductor chip is higher than the bumps.

A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.

A semiconductor device includes a first redistribution layer pattern, a second redistribution layer pattern, and a recognition mark. The first redistribution layer pattern is formed on a semiconductor substrate. The second redistribution layer pattern, with a bonding pad portion, is disposed on the first redistribution layer pattern. Furthermore, the recognition mark is formed on the first redistribution layer pattern to indicate a position of the bonding pad portion.

An integrated circuit (IC) is provided. The IC includes a molding compound, a plurality of pins, an exposed pad, a die surrounded by the molding compound, an adhesive material, and a plurality of bonding wires. The pins are disposed on at least one edge of the molding compound and separated from each other. The adhesive material is disposed between the die and the exposed pad and surrounded by the molding compound. The exposed pad is electrically connected to the die through one of the bonding wires, and the pins are electrically connected to the die through the remaining bonding wires. The die is configured to detect whether a chassis intrusion event is present in response to a signal from the exposed pad.