A driving chip and a display panel are provided. The display panel includes the driving chip, and a plurality of first bonding pads and a plurality of second bonding pads disposed at two opposite sides of the driving chip. The driving chip includes a group of first input leads and a group of second input leads. There is an interval between the group of first input leads and the group of second input leads. The group of first input leads is disposed near the first bonding pads, and the group of second input leads is disposed near the second bonding pads.

A bond pad structure and method are provided. The structure includes a first conductive layer formed over a substrate. A second conductive layer is formed over a first portion of the first conductive layer, and a first portion of the second conductive layer forms a first capacitor electrode. A third conductive layer is formed over the first conductive layer and second conductive layer, and a first portion of the third conductive layer forms a second capacitor electrode. A second portion of the third conductive layer forms a wire bond region. A dielectric material is disposed between the first capacitor electrode and the second capacitor electrode to form a first capacitor.

A semiconductor chip is mounted on a leadframe. A first portion of an insulating package for the semiconductor chip is formed from laser direct structuring (LDS) material molded onto the semiconductor chip. A conductive formation (provided by laser-drilling the LDS material and plating) extends between the outer surface of the first portion of insulating package and the semiconductor chip. An electrically conductive clip is applied onto the outer surface of the first portion of the insulating package, with the electrically conductive clip electrically coupled to the conductive formation and the leadframe. A second portion of the insulating package is made from package molding material (epoxy compound) molded onto the electrically conductive clip and applied onto the outer surface of the first portion of the insulating package.

A first wire has a first contact connected to a first semiconductor element, and a second contact connected to a second semiconductor element. A second wire has a third contact connected to the first semiconductor element and a fourth contact connected to the second semiconductor element. A first linear portion between the first contact and the second contact of the first wire has an undulation. A second linear portion between the third contact and the fourth contact of the second wire has an undulation. A first top portion of the first linear portion is adjacent to a second top portion of the second linear portion. An interval between the first top portion and the second top portion is narrower than an interval between the first contact and the third contact. The interval between the first top portion and the second top portion is narrower than an interval between the second contact and the fourth contact.

A package includes a circuit that includes at least one active area and at least one secondary device area, a support configured to support the circuit, and a die attach material. The circuit being mounted on the support using the die attach material and the die attach material including at least one channel configured to allow gases generated during curing of the die attach material to be released from the die attach material.

A semiconductor package includes a lower semiconductor die and an upper semiconductor die which are stacked with an offset in a first direction, wherein the lower semiconductor die includes a plurality of lower pads arranged in a second direction, which is perpendicular to the first direction, and wherein the upper semiconductor die includes a plurality of upper pads arranged in the second direction. The semiconductor package also includes bent wires electrically connecting the lower pads of the lower semiconductor die with the upper pads of the upper semiconductor die in the first direction. The semiconductor package further includes vertical wires such that a vertical wire is disposed on any one of the lower pad and the upper pad for each pair of pads electrically connected by a bent wire.

Apparatuses relating generally to a vertically integrated microelectronic package are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface. A first microelectronic device is coupled to the upper surface of the substrate. The first microelectronic device is a passive microelectronic device. First wire bond wires are coupled to and extend away from the upper surface of the substrate. Second wire bond wires are coupled to and extend away from an upper surface of the first microelectronic device. The second wire bond wires are shorter than the first wire bond wires. A second microelectronic device is coupled to upper ends of the first wire bond wires and the second wire bond wires. The second microelectronic device is located above the first microelectronic device and at least partially overlaps the first microelectronic device.

A semiconductor module that restrains the occurrence of detachment and an operation failure. The semiconductor module includes a PCB base, a conductive die pad provided on the PCB base, a semiconductor die provided on the conductive die pad, and a conductive die bonding agent that electrically connects the conductive die pad and the semiconductor die. The semiconductor module further includes a wire bonding pad provided on the PCB base, a wire that electrically connects the wire bonding pad and the semiconductor die, and a sealing resin that seals the conductive die pad, the semiconductor die, the conductive die bonding agent, the wire bonding pad, and the wire. In a planar view, the area of the conductive die pad is 5.0 mm.sup.2 or less.

A bond pad structure and method are provided. The structure includes a first conductive layer formed over a substrate. A second conductive layer is formed over a first portion of the first conductive layer, and a first portion of the second conductive layer forms a first capacitor electrode. A third conductive layer is formed over the first conductive layer and second conductive layer, and a first portion of the third conductive layer forms a second capacitor electrode. A second portion of the third conductive layer forms a wire bond region. A dielectric material is disposed between the first capacitor electrode and the second capacitor electrode to form a first capacitor.

A semiconductor module that restrains the occurrence of detachment and an operation failure. The semiconductor module includes a PCB base, a conductive die pad provided on the PCB base, a semiconductor die provided on the conductive die pad, and a conductive die bonding agent that electrically connects the conductive die pad and the semiconductor die. The semiconductor module further includes a wire bonding pad provided on the PCB base, a wire that electrically connects the wire bonding pad and the semiconductor die, and a sealing resin that seals the conductive die pad, the semiconductor die, the conductive die bonding agent, the wire bonding pad, and the wire. In a planar view, the area of the conductive die pad is 5.0 mm.sup.2 or less.