A driving chip and a display panel are provided. The display panel includes the driving chip, and a plurality of first bonding pads and a plurality of second bonding pads disposed at two opposite sides of the driving chip. The driving chip includes a group of first input leads and a group of second input leads. There is an interval between the group of first input leads and the group of second input leads. The group of first input leads is disposed near the first bonding pads, and the group of second input leads is disposed near the second bonding pads.

A semiconductor chip package is provided with improved connections between different components within the package. The semiconductor chip package may comprise a semiconductor chip disposed on a substrate. The semiconductor chip may have a first surface and a second surface. The first surface of the semiconductor chip may be connected to the substrate. The semiconductor chip package may comprise a leadframe that includes a first lead and a second lead. The first lead of the leadframe may be directly attached to the second surface of the semiconductor chip. The second lead of the leadframe may be directly attached to the substrate.

A semiconductor chip package is provided with improved connections between different components within the package. The semiconductor chip package may comprise a semiconductor chip disposed on a substrate. The semiconductor chip may have a first surface and a second surface. The first surface of the semiconductor chip may be connected to the substrate. The semiconductor chip package may comprise a leadframe that includes a first lead and a second lead. The first lead of the leadframe may be directly attached to the second surface of the semiconductor chip. The second lead of the leadframe may be directly attached to the substrate.

A multi-chip module structure (MCM) having improved heat dissipation includes a plurality of semiconductor chips having a front side mounted on a packaging substrate, wherein each semiconductor chip of the plurality of semiconductor chips further includes a through-substrate vias located at a backside of each semiconductor chip of the plurality of semiconductor chips. A plurality of wire bonds is present that provides interconnect between each semiconductor chip of the plurality of semiconductor chips and is located at the backside of each semiconductor chip of the plurality of semiconductor chips. A heat sink is located above a gap containing the plurality of wire bonds, and a cooling element is located on a surface of the heat sink.

A device includes an enclosure cover; a chip carrier attachable to and removable from the enclosure cover; and a ridge gap waveguide (RGW) cover. The chip carrier includes at least two cavities disposed on one surface and located on opposite sides, and each cavity has a slot extending to an opposite surface of the chip carrier. The RGW cover includes a plurality of ridges and a plurality of pillars disposed on one surface. The enclosure cover and the RGW cover are configured to connect to each other with the chip carrier located therebetween, and the opposite surface of the chip carrier faces the one surface of the RGW cover when the enclosure cover and the RGW cover are connected.

A semiconductor device is disclosed including a wire bonded die stack where the bond wires skip dies in the die stack to provide bond wires having a long length. In one example, the semiconductor dies are stacked on top of each other with offsets along two orthogonal axes so that the dies include odd numbered dies interspersed and staggered with respect to even numbered dies only one of the axes. Wire bonds may be formed between the odd numbered dies, skipping the even numbered dies, and wire bonds may be formed between the even numbered dies, skipping the odd numbered dies. The long length of the bond wires increases an inductance of the wire bonds relative to parasitic capacitance of the semiconductor dies, thereby increasing signal path bandwidth of the semiconductor device.

Disclosed herein are testing apparatus and methods to identify latent defects in IC devices based on capacitive coupling between bond wires. Bond wires may have latent defects that do not appear as hard shorts or hard opens at the time of testing, but may pose a high risk of developing into hard shorts or hard opens over time. A latent defect may form when two adjacent bond wires are disturbed to become close to each other. According to some embodiments, capacitive coupling between a pair of pins may be used to provide an indication of a near-short latent defect between bond wires connected to the pair of pins.

The object of the present invention is to provide a semiconductor device capable of reducing the influence of gas generated from a resin to which a fire retardant is not added, and a power conversion device including the semiconductor device. The semiconductor device according to the present invention includes: a semiconductor element disposed on an insulating substrate; a case disposed around an outer edge of the insulating substrate, the case including an opening facing the semiconductor element; a sealing resin sealing the semiconductor element in the case; and a lid closing the opening of the case, wherein the sealing resin does not contain a fire retardant, the lid contains the fire retardant, and a space is provided between the sealing resin and the lid.

A semiconductor device comprises a leadframe comprising a die pad and a plurality of leads, a semiconductor die disposed on the die pad, the semiconductor die including a contact pad on a first main face thereof, and one or more bond wires connected with the contact pad, wherein a lead of the plurality of leads is bent back and connected with at least one first bond wire of the one or more bond wires.

A microelectronic device includes a galvanic isolation device on a silicon substrate and a semiconductor device on a semiconductor substrate. The galvanic isolation device includes a lower isolation element over the silicon substrate and an upper isolation element above the lower isolation element, separated by a dielectric plateau that comprises inorganic dielectric material extending from the lower isolation element to the upper isolation element. The galvanic isolation device includes lower bond pads connected to the lower isolation element adjacent to the dielectric plateau, and upper bond pads over the dielectric plateau, connected to the upper isolation element. The semiconductor device includes an active component, and device bond pads coupled to the active component. The microelectronic device includes first electrical connections to the lower bond pads and second electrical connections to the upper bond pads. The first electrical connections or the second electrical connections are connected to the device bond pads.