In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and the source that are located on a first surface of the second die and a drain that is located on a second surface of the second die that is opposite the first surface.

A semiconductor light-emitting diode (LED) package is provided and includes a semiconductor LED chip having a surface on which a first electrode and a second electrode are formed; a first solder bump formed on the first electrode and a second solder bump formed on the second electrode, the first solder bump and the second solder bump protruding from the surface of the semiconductor LED chip; and a resin layer having a bottom portion that surrounds a first side surface of the first solder bump and a second side surface of the second solder bump and covers the surface of the semiconductor LED chip.

Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

A semiconductor device is disclosed including at least first and second vertically stacked and interconnected semiconductor packages. Signal communication between the second semiconductor package and a host device occurs through the first semiconductor package.

A semiconductor light-emitting diode (LED) package is provided and includes a semiconductor LED chip having a surface on which a first electrode and a second electrode are formed; a first solder bump formed on the first electrode and a second solder bump formed on the second electrode, the first solder bump and the second solder bump protruding from the surface of the semiconductor LED chip; and a resin layer having a bottom portion that surrounds a first side surface of the first solder bump and a second side surface of the second solder bump and covers the surface of the semiconductor LED chip.

A semiconductor package may be composed of a variety of different types of semiconductor chips of different sizes and support structures stacked within the semiconductor package. Semiconductor chips having a larger chip size may be stacked above smaller semiconductor chips. Smaller chips may be included in a layer of the semiconductor package along with a support structure which may assist supporting upper semiconductor chips, such as during a wire bonding process connecting bonding wires to chip pads of the semiconductor chips above the support structure. Use of different thicknesses of die attach film may allow for a further reduction in height of the semiconductor package. When implemented as a package housing a memory controller, DRAM semiconductor chips and non-volatile memory chips, locating the memory controller in a lower layer of the semiconductor package facilitates usage of the package substrate as a redistribution layer to provide communications between the memory controller and the DRAM and non-volatile memory chips.

Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

A packaging structure is provided, including a substrate, a first chip, a second chip, and a conductive unit. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip by the conductive unit.

A semiconductor device is disclosed including at least first and second vertically stacked and interconnected semiconductor packages. Signal communication between the second semiconductor package and a host device occurs through the first semiconductor package.