Patent classifications
H01L2224/4911
SEMICONDUCTOR DEVICE
Provided is a semiconductor device applicable to both types of packages regardless of whether or not double bonding of a lead frame pad is allowed. The semiconductor device includes: an operational amplifier; a feedback resistor; a reference voltage generation circuit; an output transistor; a first pad which is connected to an output terminal of the output transistor, and is to be selectively connected to a lead frame pad by a bonding wire; a second pad to be selectively connected to the lead frame pad by a bonding wire; and a connection switching element provided between the first pad and the second pad. In a case in which the second pad is connected to the lead frame pad by the bonding wire, the connection switching element interrupts connection between the first pad and the second pad.
SYSTEM AND METHOD FOR REDUCING MUTUAL COUPLING FOR NOISE REDUCTION IN SEMICONDUCTOR DEVICE PACKAGING
A mechanism is provided to reduce noise effects on signals traversing bond wires of a SOC by forming a bond wire ring structure that decreases mutual inductance and capacitive coupling. Bond wires form the ring structure in a daisy chain connecting isolated ground leads at a semiconductor device package surrounding the semiconductor device. This structure reduces out-of-plane electromagnetic field interference generated by signals in lead wires, as well as mutual capacitance and mutual inductance.
Doherty amplifier
A package (1) includes first and second input terminals (2,3) which are adjacent to each other, and first and second output terminals (4,5) which are adjacent to each other. A first input matching circuit (6), a first delay circuit (7), a second input matching circuit (8), a first amplifier (9), and a first output matching circuit (10) are sequentially connected between the first input terminal (2) and the first output terminal (4) inside the package (1). A third input matching circuit (11), a second amplifier (12), a second output matching circuit (13), a second delay circuit (14), and a third output matching circuit (15) are sequentially connected between the second input terminal (3) and the second output terminal (5) inside the package (1). First to fourth matching circuits (16-19) are respectively connected to the first input terminal (2), the second input terminal (3), the first output terminal (4) and the second output terminal (5) outside the package (1).
Silicon carbide device and method for forming a silicon carbide device
A silicon carbide device includes a silicon carbide substrate, a contact layer including nickel, silicon and aluminum, a barrier layer structure including titanium and tungsten, and a metallization layer including copper. The contact layer is located on the silicon carbide substrate. The contact layer is located between the silicon carbide substrate and at least a part of the barrier layer structure. The barrier layer structure is located between the silicon carbide substrate and the metallization layer.
SEMICONDUCTOR DEVICE
A semiconductor device includes: a semiconductor substrate having a first main surface; an aluminum electrode having a first surface facing the first main surface and a second surface opposite to the first surface, the aluminum electrode being disposed on the semiconductor substrate; a passivation film that covers a peripheral edge of the second surface and that is provided with an opening from which a portion of the second surface is exposed; a copper film disposed on the second surface exposed from the opening so as to be separated from the passivation film; and a metal film disposed on the second surface exposed from between the passivation film and the copper film. The metal film is constituted of at least one selected from a group consisting of a nickel film, a tantalum film, a tantalum nitride film, a tungsten film, a titanium film, and a titanium nitride film.
SEMICONDUCTOR DEVICE
A semiconductor device of the present disclosure includes: a semiconductor substrate having a first main surface; a first aluminum electrode having a first surface facing the first main surface and a second surface opposite to the first surface, the first aluminum electrode being disposed on the semiconductor substrate; a passivation film that covers a peripheral edge of the second surface and that is provided with an opening from which a portion of the second surface is exposed; and a copper film. The second surface exposed from the opening is provided with a recess that is depressed toward the first surface. The copper film is disposed in the recess.
Bottom package exposed die MEMS pressure sensor integrated circuit package design
A MEMS pressure sensor packaged with a molding compound. The MEMS pressure sensor features a lead frame, a MEMS semiconductor die, a second semiconductor die, multiple pluralities of bonding wires, and a molding compound. The MEMS semiconductor die has an internal chamber, a sensing component, and apertures. The MEMS semiconductor die and the apertures are exposed to an ambient atmosphere. A method is desired to form a MEMS pressure sensor package that reduces defects caused by mold flashing and die cracking. Fabrication of the MEMS pressure sensor package comprises placing a lead frame on a lead frame tape; placing a MEMS semiconductor die adjacent to the lead frame and on the lead frame tape with the apertures facing the tape and being sealed thereby; attaching a second semiconductor die to the MEMS semiconductor die; attaching pluralities of bonding wires to form electrical connections between the MEMS semiconductor die, the second semiconductor die, and the lead frame; and forming a molding compound.
Power semiconductor device including press-fit connection terminal
A power semiconductor device includes: a power semiconductor element; a control circuit that controls the power semiconductor element; a control substrate having the control circuit mounted thereon; a lid arranged to overlap with at least a portion of the control substrate in a first direction; and at least one external connection terminal having a first portion connected with the control substrate, a second portion to be connected with an external apparatus, and a third portion located between the first portion and the second portion and fixed to the lid, the first portion being constituted as a press-fit portion.
Optical subassembly
Provided is an optical subassembly, which is compact, is easy to manufacture, and has satisfactory high-frequency characteristics. The optical subassembly includes: an eyelet including a first surface, a second surface and a plurality of through-holes; a plurality of lead terminals; a relay substrate including a lead connection surface and a first bonding surface and having first and second conductor patterns formed across the lead connection surface and the first bonding surface; a device mounting unit including a second bonding surface having formed thereon third and fourth conductor patterns; and an optical device configured to convert one of an optical signal and the differential electrical signals into the other. The first and second conductor patterns on the first bonding surface are connected to the third and fourth conductor patterns by bonding wires, respectively, and the first and second bonding surfaces have normal directions in the same direction.
DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF
A display apparatus includes a support substrate, a plurality of light emitting structures regularly arranged on the support substrate, and a wavelength conversion part disposed on the plurality of light emitting structures. The wavelength conversion part includes light transmitting portions and blocking portions, the light transmitting portions being disposed on the light emitting structures, respectively, and each of the light transmitting portions including a phosphor for converting a wavelength of light emitted from the corresponding light emitting structure. The support substrate includes a plurality of conductive patterns electrically connected to the light emitting structures, and the light emitting structures are coupled to the plurality of conductive patterns.