A semiconductor assembly includes a power semiconductor, a housing containing the power semiconductor, and electrically conductive channels. The electrically conductive channels are arranged to direct coolant through the housing. Heat generated by the power semiconductor can therefore be absorbed by the coolant. The electrically conductive channels are also electrically connected with the power semiconductor to form terminals for the power semiconductor.

Semiconductor devices may include a substrate and a backside-biased semiconductor die supported above the substrate. A backside surface of the backside-biased semiconductor die may be spaced from the substrate. The backside surface may be electrically connected to ground by wire bonds extending to the substrate. Methods of making semiconductor devices may involve supporting a backside-biased semiconductor die supported above a substrate, a backside surface of the backside-biased semiconductor die being spaced from the substrate. The backside surface may be electrically connected to ground by wire bonds extending to the substrate. Systems may include a sensor device, a nontransitory memory device, and at least one semiconductor device operatively connected thereto. The at least one semiconductor device may include a substrate and a backside-biased semiconductor die supported above the substrate. A backside surface of the backside-biased semiconductor die may be electrically connected to ground by wire bonds extending to the substrate.

A semiconductor chip includes a substrate including a circuit area having a rectangular shape and a peripheral area surrounding the circuit area, a key area being overlapping a part of the circuit area and a part of the peripheral area, a plurality of drive circuit cells in the circuit area, and a conductive reference line on the peripheral area and extending in a first direction parallel to a first edge among four edges of the rectangular shape of the circuit area.

The present invention addresses the problem of enlarging a sensing area in an ultrasonic probe so as to achieve a higher definition. This ultrasonic diagnostic equipment is provided with an ultrasonic probe that comprises: a CMUT chip (2a) that has drive electrodes (3e)-(3j), etc., arranged in a grid-like configuration on a rectangular CMUT element section (21); and a CMUT chip (2b) that has drive electrodes (3p)-(3u), etc., arranged in a grid-like configuration on the rectangular CMUT element section (21), that is adjacent to the CMUT chip (2a), and in which the drive electrodes (3e)-(3j) of the adjacent CMUT chip (2a) are electrically connected to the respective drive electrodes (3p)-(3u) via bonding wires (4f)-(4i), etc.

Various chip stack power delivery circuits are disclosed. In one aspect, an apparatus is provided that includes a stack of semiconductor chips that has an uppermost semiconductor chip and a lowermost semiconductor chip. A heat spreader is positioned on the uppermost semiconductor chip. A power transfer circuit is configured to transfer electric power from the heat spreader to the uppermost semiconductor chip.

An integrated circuit (IC) device may include a substrate having an active device layer. The integrated circuit may also include a first defect layer. The first defect layer may have a first surface facing a backside of the active device layer. The integrated circuit may further include a second defect layer. The second defect layer may face a second surface opposite the first surface of the first defect layer.

A semiconductor arrangement includes a controllable semiconductor element having an active region, and bonding wires arranged in parallel to each other in a first horizontal direction. The active region has a first length in the first horizontal direction and a first width in a second horizontal direction perpendicular to the first horizontal direction. Each bonding wire is electrically and mechanically coupled to the controllable semiconductor element by a first number of bond connections arranged above the active region. A first bond connection of each bonding wire is arranged at a first distance from a first edge of the active region. A second bond connection of each bonding wire is arranged at a second distance from a second edge of the active region opposite the first edge. The first and second distances are both less than the first length divided by twice the first number of bond connections.

Various chip stack power delivery circuits are disclosed. In one aspect, an apparatus is provided that includes a stack of semiconductor chips that has an uppermost semiconductor chip and a lowermost semiconductor chip. A heat spreader is positioned on the uppermost semiconductor chip. A power transfer circuit is configured to transfer electric power from the heat spreader to the uppermost semiconductor chip.

A light emitting device can include a light emitting structure including a p-GaN based semiconductor layer, an active layer having multiple quantum wells, and an n-GaN based semiconductor layer; a p-electrode and an n-electrode electrically connecting with the light emitting structure, respectively, wherein the n-electrode has a plurality of layers; a first passivation layer including a first portion contacting a portion of the n-electrode, a second portion vertically overlapped with the p-electrode, and a third portion that extends outside of outermost side surfaces of the light emitting structure; a phosphor layer disposed on a top surface of the light emitting structure; and a second passivation layer including a first portion disposed between the phosphor layer and the top surface of the light emitting structure, and a second portion disposed on the outermost side surfaces of the light emitting structure, in which the phosphor layer includes a pattern to bond a wire with a p-pad on a portion of the p-electrode, the second portion of the second passivation layer extends toward the third portion of the first passivation and contacts the third portion of the first passivation layer, and the first passivation layer includes an opening on the n-GaN based semiconductor layer such that the opening accommodates at least a portion of the n-electrode.

Quantum computing assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a quantum computing assembly may include a plurality of dies electrically coupled to a package substrate, and lateral interconnects between different dies of the plurality of dies, wherein the lateral interconnects include a superconductor, and at least one of the dies of the plurality of dies includes quantum processing circuitry.