A semiconductor device has a substrate. A plurality of conductive vias is formed through the substrate. A conductive layer is formed over the substrate. An insulating layer is formed over conductive layer. A portion of the substrate is removed to expose the conductive vias. A plurality of vertical interconnect structures is formed over the substrate. A first semiconductor die is disposed over the substrate. A height of the vertical interconnect structures is less than a height of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and the vertical interconnect structures. A first portion of the encapsulant is removed from over the first semiconductor die while leaving a second portion of the encapsulant over the vertical interconnect structures. The second portion of the encapsulant is removed to expose the vertical interconnect structures. A second semiconductor die is disposed over the first semiconductor die.

A method of manufacturing a semiconductor device includes: receiving a first substrate with a surface; receiving a second substrate; determining a pad array on the surface of the first substrate, wherein the pad array includes a first type pad and a second type pad; forming a via pattern underlying the pad array in the first substrate according to the location of each via, wherein the first type pad in the pad array is directly contacting a via of the via pattern and the second type pad in the pad array is clear of any via of the via pattern; laterally connecting the second type pad with a conductive trace, wherein the conductive trace connects to another via that is same level with the via contacting the first type pad; and disposing a first conductive bump and a second conductive bump between the first substrate and the second substrate.

A display device and chip bonding method thereof are provided. The display device includes a flexible display panel and a chip bonded to the non-display area of the flexible display panel with the extension directions of individual bumps satisfying, depending on the area in which the bumps are located, the following requirements: in each row of bumps, at least the individual bumps in lateral zones have their extension lines on the same side converging at a same point on the reference line, and the two bumps belong to a same bump group have their extension lines respectively forming an angle with respect to the reference line, the angles being equal to each other.

A lead-free solder alloy having a low melting temperature and low yield strength is disclosed. The solder alloy includes 5.0-20.0 wt. % of indium (In), 1.0-5.0 wt. % of silver (Ag), 0.25-2.0 wt. % of copper (Cu), 0.1-0.5 wt. % of zinc (Zn), and a remainder of tin (Sn). In implementations, a sulfur compound may be included in a concentration of 100 ppm to 500 ppm in the alloy to prevent oxidation of zinc and indium on the surface of the alloy. The solder alloy is particularly useful for but not limited to solder on pad applications in first level interconnect semiconductor device packaging.

A method for aligning a chip onto a substrate is disclosed. The method includes, depositing a ferrofluid, onto a substrate that has one or more pads that electrically couple to a semiconductor layer. The method can include a chip with solder balls electrically coupled to the logic elements of the chip, which can be placed onto the deposited ferrofluid, where the chip is supported on the ferrofluid, in a substantially coplanar orientation to the substrate. The method can include determining if the chip is misaligned from a desired location on the substrate. The method can include adjusting the current location of the chip in response to determining that the solder balls of the chip are misaligned from the desired location on the pads of the substrate, until the chip is aligned in the desired location.

A system for determining thickness variation values of a semiconductor substrate comprises a substrate vacuumed to a pedestal that defines a reference plane for measuring the substrate. A measurement probe assembly determines substrate CTV and BTV values, and defines a substrate slope angle. A thermal bonding assembly attaches a die to the substrate at a bonding angle congruent with the substrate slope angle. A plurality of substrates are measured using the same reference plane on the pedestal. Associated methods and processes are disclosed.

A three-dimensional mounting method for successively laminating N number of upper-layer joining materials includes positioning a first upper-layer joining material relative to a lowermost-layer joining material by recognizing an alignment position of the lowermost-layer joining material and a lower face alignment position of the first upper-layer joining material by a two-field image recognition unit, storing positional coordinates of the alignment position of the lowermost-layer joining material, positioning an (n+1)-th upper-layer joining material relative to an n-th upper-layer joining material by recognizing an upper face alignment position of the n-th upper-layer joining material and a lower face alignment position of the (n+1)-th upper-layer joining material, storing positional coordinates of the upper face alignment position of the n-th upper-layer joining material, recognizing an upper face alignment position of the N-th uppermost-layer joining material, and storing positional coordinates of the upper face alignment position of the N-th uppermost-layer joining material.

Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.

The invention concerns a method of flip-chip assembly between first (1) and second (2) components each comprising connection pads (11, 21) on one of the faces of same, referred to as assembly faces, which involves transferring the components onto each other via the assembly faces of same in such a way as to create electrical interconnections between the pads of the first and second components. The invention involves transforming the copper oxide into copper by UV annealing, very locally, in the gap between the components, at least around the areas adjacent to the connection pads. The method according to the invention can be used for any component that is transparent to UV rays, including for substrates made from a plastic material such as substrates made from PEN or PET. The invention also concerns the assembly of two components obtained by the method.

Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.