A method of forming a semiconductor package. Implementations include forming on a die backside an intermediate metal layer having multiple sublayers, each including a metal selected from the group consisting of titanium, nickel, copper, silver, and combinations thereof. A tin layer is deposited onto the intermediate metal layer and is then reflowed with a silver layer of a substrate to form an intermetallic layer having a melting temperature above 260 degrees Celsius and including an intermetallic consisting of silver and tin and/or an intermetallic consisting of copper and tin. Another method of forming a semiconductor package includes forming a bump on each of a plurality of exposed pads of a top side of a die, each exposed pad surrounded by a passivation layer, each bump including an intermediate metal layer as described above and a tin layer coupled to the intermediate metal layer is reflowed to form an intermetallic layer.

An interconnection layer carrying structure for transferring an interconnection layer onto a substrate is disclosed. The interconnection layer carrying structure includes a support substrate, a release layer on the support substrate; and an interconnection layer on the release layer. The interconnection layer includes an organic insulating material and a set of pads embedded in the organic insulating material. The set of the pads is configured to face towards the support substrate. The support substrate has a base part where the interconnection layer is formed and an extended part extending outside the base part.

An interconnection layer carrying structure for transferring an interconnection layer onto a substrate is disclosed. The interconnection layer carrying structure includes a support substrate, a release layer on the support substrate; and an interconnection layer on the release layer. The interconnection layer includes an organic insulating material and a set of pads embedded in the organic insulating material. The set of the pads is configured to face towards the support substrate. The support substrate has a base part where the interconnection layer is formed and an extended part extending outside the base part.

A first conductive pad is connected to a second conductive pad by using a post-transition metal and a nanoporous metal. An example of the post-transition metal is indium. An example of the nanoporous metal is nanoporous gold. A block of the post-transition metal is formed on the first conductive pad. The block of the post-transition metal is coated with a layer of anti-corrosion material. A block of the nanoporous metal is formed on the second conductive pad. The block of the post-transition metal and the block of the nanoporous metal are thermal compressed to form an alloy between the first conductive pad and the second conductive pad.

Connector structures and methods of forming the same are provided. A method includes forming a first patterned passivation layer on a workpiece, the first patterned passivation layer having a first opening exposing a conductive feature of the workpiece. A seed layer is formed over the first patterned passivation layer and in the first opening. A patterned mask layer is formed over the seed layer, the patterned mask layer having a second opening exposing the seed layer, the second opening overlapping with the first opening. A connector is formed in the second opening. The patterned mask layer is partially removed, an unremoved portion of the patterned mask layer remaining in the first opening. The seed layer is patterned using the unremoved portion of the patterned mask layer as a mask.

Connector structures and methods of forming the same are provided. A method includes forming a first patterned passivation layer on a workpiece, the first patterned passivation layer having a first opening exposing a conductive feature of the workpiece. A seed layer is formed over the first patterned passivation layer and in the first opening. A patterned mask layer is formed over the seed layer, the patterned mask layer having a second opening exposing the seed layer, the second opening overlapping with the first opening. A connector is formed in the second opening. The patterned mask layer is partially removed, an unremoved portion of the patterned mask layer remaining in the first opening. The seed layer is patterned using the unremoved portion of the patterned mask layer as a mask.

Embodiments of the disclosure relate to an MIO substrate with integrated jet cooling for electronic modules and a method of forming the same. In one embodiment, a substrate for an electronic module includes a thermal compensation base layer having an MIO structure and a cap layer overgrown on the MIO structure. A plurality of orifices extends through the thermal compensation base layer between an inlet face and an outlet face positioned opposite to the inlet face, defining a plurality of jet paths. A plurality of integrated posts extends outward from the cap layer, wherein each integrated post of the plurality of integrated posts is positioned on the outlet face between each orifice of the plurality of orifices.

Embodiments of the disclosure relate to an MIO substrate with integrated jet cooling for electronic modules and a method of forming the same. In one embodiment, a substrate for an electronic module includes a thermal compensation base layer having an MIO structure and a cap layer overgrown on the MIO structure. A plurality of orifices extends through the thermal compensation base layer between an inlet face and an outlet face positioned opposite to the inlet face, defining a plurality of jet paths. A plurality of integrated posts extends outward from the cap layer, wherein each integrated post of the plurality of integrated posts is positioned on the outlet face between each orifice of the plurality of orifices.

A display device including a display area and a non-display area disposed around the display area. The device includes a substrate; and at least one pad terminal disposed in the non-display area on the substrate and including an uneven surface in which concave portions and convex portion are electrically connected to each other.

Connector structures and methods of forming the same are provided. A method includes forming a first patterned passivation layer on a workpiece, the first patterned passivation layer having a first opening exposing a conductive feature of the workpiece. A seed layer is formed over the first patterned passivation layer and in the first opening. A patterned mask layer is formed over the seed layer, the patterned mask layer having a second opening exposing the seed layer, the second opening overlapping with the first opening. A connector is formed in the second opening. The patterned mask layer is partially removed, an unremoved portion of the patterned mask layer remaining in the first opening. The seed layer is patterned using the unremoved portion of the patterned mask layer as a mask.