There is provided a bonding paste capable of forming a uniform bonding layer by reducing occurrence of voids at edges even when a bonding area is large, and bonding method using the paste, and provides a metal paste for bonding containing at least metal nanoparticles (A) having a number average primary particle size of 10 to 100 nm, wherein a cumulative weight loss value (L.sub.100) when a temperature is raised from 40° C. to 100° C. is 75 or less, and a cumulative weight loss value (L.sub.150) when a temperature is raised from 40° C. to 150° C. is 90 or more, and a cumulative weight loss value (L.sub.200) when a temperature is raised from 40° C. to 200° C. is 98 or more, based on 100 cumulative weight loss value (L.sub.700) when the paste is heated from 40° C. to 700° C. at a heating rate of 3° C./min in a nitrogen atmosphere.

There is provided a bonding paste capable of forming a uniform bonding layer by reducing occurrence of voids at edges even when a bonding area is large, and bonding method using the paste, and provides a metal paste for bonding containing at least metal nanoparticles (A) having a number average primary particle size of 10 to 100 nm, wherein a cumulative weight loss value (L.sub.100) when a temperature is raised from 40° C. to 100° C. is 75 or less, and a cumulative weight loss value (L.sub.150) when a temperature is raised from 40° C. to 150° C. is 90 or more, and a cumulative weight loss value (L.sub.200) when a temperature is raised from 40° C. to 200° C. is 98 or more, based on 100 cumulative weight loss value (L.sub.700) when the paste is heated from 40° C. to 700° C. at a heating rate of 3° C./min in a nitrogen atmosphere.

Process for producing an electronic subassembly by low-temperature pressure sintering, comprising the following steps: arranging an electronic component on a circuit carrier having a conductor track, connecting the electronic component to the circuit carrier by the low-temperature pressure sintering of a joining material which connects the electronic component to the circuit carrier, characterized in that, to avoid the oxidation of the electronic component or of the conductor track, the low-temperature pressure sintering is carried out in a low-oxygen atmosphere having a relative oxygen content of 0.005 to 0.3%.

A sintering press to sinter electronic components on a substrate comprises a pressing unit comprising a multi-rod cylinder having a front head and a rear head which jointly delimit a compression chamber. In the front head, presser rods parallel and independent of each other are slidingly supported. Each presser rod is coaxial and barycentric to a respective electronic component to be sintered and has a thrust section proportional to the force to be applied to the respective electronic component. In the compression chamber a sealing membrane extends, which is deformed so as to abut against the presser rods for transferring the sintering pressure on each presser rod.

An integrated circuit structure is provided. The integrated circuit structure includes a die that contains a substrate, an interconnection structure, active connectors and dummy connectors. The interconnection structure is disposed over the substrate. The active connectors and the dummy connectors are disposed over the interconnection structure. The active connectors are electrically connected to the interconnection structure, and the dummy connectors are electrically insulated from the interconnection structure.

An integrated circuit structure is provided. The integrated circuit structure includes a die that contains a substrate, an interconnection structure, active connectors and dummy connectors. The interconnection structure is disposed over the substrate. The active connectors and the dummy connectors are disposed over the interconnection structure. The active connectors are electrically connected to the interconnection structure, and the dummy connectors are electrically insulated from the interconnection structure.

The present disclosure relates to a method for manufacturing a semiconductor package including vacuum-laminating a non-conductive film on a substrate on which a plurality of through silicon vias are provided and bump electrodes are formed, and then performing UV irradiation, wherein an increase in melt viscosity before and after UV irradiation can be adjusted to 30% or less, whereby a bonding can be performed without voids during thermo-compression bonding, and resin-insertion phenomenon between solders can be prevented, fillets can be minimized and reliability can be improved.

Methods for attachment and devices produced using such methods are disclosed. In certain examples, the method comprises disposing a capped nanomaterial on a substrate, disposing a die on the disposed capped nanomaterial, drying the disposed capped nanomaterial and the disposed die, and sintering the dried disposed die and the dried capped nanomaterial at a temperature of 300° C. or less to attach the die to the substrate. Devices produced using the methods are also described.

A semiconductor device manufacturing method includes a preparation step and a sinter bonding step. In the preparation step, a sinter-bonding work having a multilayer structure including a substrate, semiconductor chips, and sinter-bonding material layers is prepared. The semiconductor chips are disposed on, and will bond to, one side of the substrate. Each sinter-bonding material layer contains sinterable particles and is disposed between each semiconductor chip and the substrate. In the sinter bonding step, a cushioning sheet having a thickness of 5 to 5000 μm and a tensile elastic modulus of 2 to 150 MPa is placed on the sinter-bonding work, the resulting stack is held between a pair of pressing faces, and, in this state, the sinter-bonding work between the pressing faces undergoes a heating process while being pressurized in its lamination direction, to form a sintered layer from each sinter-bonding material layer.

A semiconductor device manufacturing method includes a preparation step and a sinter bonding step. In the preparation step, a sinter-bonding work having a multilayer structure including a substrate, semiconductor chips, and sinter-bonding material layers is prepared. The semiconductor chips are disposed on, and will bond to, one side of the substrate. Each sinter-bonding material layer contains sinterable particles and is disposed between each semiconductor chip and the substrate. In the sinter bonding step, a cushioning sheet having a thickness of 5 to 5000 μm and a tensile elastic modulus of 2 to 150 MPa is placed on the sinter-bonding work, the resulting stack is held between a pair of pressing faces, and, in this state, the sinter-bonding work between the pressing faces undergoes a heating process while being pressurized in its lamination direction, to form a sintered layer from each sinter-bonding material layer.