One aspect of the invention is a method of manufacturing a connection structure, including disposing an adhesive layer between a first electronic member including a first substrate and a first electrode formed on the first substrate and a second electronic member including a second substrate and a second electrode formed on the second substrate, and pressure-bonding the first electronic member and the second electronic member via the adhesive layer such that the first electrode and the second electrode are electrically connected to each other, wherein the first electronic member further including an insulating layer formed on a side of the first electrode opposite to the first substrate, and the adhesive layer including: a first conductive particle being a dendritic conductive particle; and a second conductive particle being a conductive particle other than the first conductive particle and having a non-conductive core and a conductive layer provided on the core.

In a semiconductor device, a first outer edge of a conductive pattern is located between the outermost edge of a first dimple and the innermost edge of a second dimple in a cross-sectional view of the device. When thermal stress due to temperature changes in the semiconductor device is applied to the ceramic circuit board, the first and second dimples suppress deformation of the ceramic circuit board that is caused due to the temperature changes. As a result, cracks in the ceramic circuit board and separation of the metal plate and the conductive pattern are prevented.

In a semiconductor device, a first outer edge of a conductive pattern is located between the outermost edge of a first dimple and the innermost edge of a second dimple in a cross-sectional view of the device. When thermal stress due to temperature changes in the semiconductor device is applied to the ceramic circuit board, the first and second dimples suppress deformation of the ceramic circuit board that is caused due to the temperature changes. As a result, cracks in the ceramic circuit board and separation of the metal plate and the conductive pattern are prevented.

A semiconductor includes a semiconductor element, a connecting terminal electrically connected to the semiconductor element, and a case including an opening space for housing the semiconductor element, a frame which surrounds the opening space and in which the connecting terminal is partially embedded, and a terminal arrangement portion protruding from the frame towards the opening space. The connecting terminal includes an internal terminal portion that extends towards the opening space with respect to the frame, the internal terminal portion having a front surface that is electrically connected to the semiconductor element and exposed to the opening space, and a rear surface that is fixed to the terminal arrangement portion.

A semiconductor includes a semiconductor element, a connecting terminal electrically connected to the semiconductor element, and a case including an opening space for housing the semiconductor element, a frame which surrounds the opening space and in which the connecting terminal is partially embedded, and a terminal arrangement portion protruding from the frame towards the opening space. The connecting terminal includes an internal terminal portion that extends towards the opening space with respect to the frame, the internal terminal portion having a front surface that is electrically connected to the semiconductor element and exposed to the opening space, and a rear surface that is fixed to the terminal arrangement portion.

A power electronics assembly includes a substrate, a semiconductor device and a metal inverse opal (MIO) bonding layer positioned between and bonded to the substrate and the semiconductor device. A first electrode is disposed on a first surface, a second electrode is disposed on a second surface, and a third electrode is disposed on a third surface. The first surface may be a top surface of the semiconductor device, the second surface may be a bottom surface of the semiconductor device, the third surface may be spaced apart from the bottom surface of the semiconductor device, and the second electrode is in electrical communication with the third electrode through the MIO bonding layer. A cooling fluid circuit with a cooling fluid inlet, a cooling fluid outlet and a cooling fluid path through the MIO bonding layer may be included.

A power electronics assembly includes a substrate, a semiconductor device and a metal inverse opal (MIO) bonding layer positioned between and bonded to the substrate and the semiconductor device. A first electrode is disposed on a first surface, a second electrode is disposed on a second surface, and a third electrode is disposed on a third surface. The first surface may be a top surface of the semiconductor device, the second surface may be a bottom surface of the semiconductor device, the third surface may be spaced apart from the bottom surface of the semiconductor device, and the second electrode is in electrical communication with the third electrode through the MIO bonding layer. A cooling fluid circuit with a cooling fluid inlet, a cooling fluid outlet and a cooling fluid path through the MIO bonding layer may be included.

A power electronics assembly includes a substrate, a semiconductor device and a metal inverse opal (MIO) bonding layer positioned between and bonded to the substrate and the semiconductor device. A first electrode is disposed on a first surface, a second electrode is disposed on a second surface, and a third electrode is disposed on a third surface. The first surface may be a top surface of the semiconductor device, the second surface may be a bottom surface of the semiconductor device, the third surface may be spaced apart from the bottom surface of the semiconductor device, and the second electrode is in electrical communication with the third electrode through the MIO bonding layer. A cooling fluid circuit with a cooling fluid inlet, a cooling fluid outlet and a cooling fluid path through the MIO bonding layer may be included.

A power electronics assembly includes a substrate, a semiconductor device and a metal inverse opal (MIO) bonding layer positioned between and bonded to the substrate and the semiconductor device. A first electrode is disposed on a first surface, a second electrode is disposed on a second surface, and a third electrode is disposed on a third surface. The first surface may be a top surface of the semiconductor device, the second surface may be a bottom surface of the semiconductor device, the third surface may be spaced apart from the bottom surface of the semiconductor device, and the second electrode is in electrical communication with the third electrode through the MIO bonding layer. A cooling fluid circuit with a cooling fluid inlet, a cooling fluid outlet and a cooling fluid path through the MIO bonding layer may be included.

A conductive plate includes a first slit formed in the space between a first chip area and a second chip area, a second slit formed in the space between the first chip area and a terminal area, and a third slit formed in the space between the second chip area and the terminal area. The first slit is a continuous line that penetrates through the conductive plate, whereas the second and third slits are continuous lines that do not penetrate through the conductive plate.