Patent classifications
H01L2224/83488
Light emitting device and fluidic manufacture thereof
Light emitting devices and methods for their manufacture are provided. According to one aspect, a light emitting device is provided that comprises a substrate having a recess, and an interlayer dielectric layer located on the substrate. The interlayer dielectric layer may have a first hole and a second hole, the first hole opening over the recess of the substrate. The light emitting device may further include first and second micro LEDs, the first micro LED having a thickness greater than the second micro LED. The first micro LED and the second micro LED may be placed in the first hole and the second hole, respectively.
Light emitting device and fluidic manufacture thereof
Light emitting devices and methods for their manufacture are provided. According to one aspect, a light emitting device is provided that comprises a substrate having a recess, and an interlayer dielectric layer located on the substrate. The interlayer dielectric layer may have a first hole and a second hole, the first hole opening over the recess of the substrate. The light emitting device may further include first and second micro LEDs, the first micro LED having a thickness greater than the second micro LED. The first micro LED and the second micro LED may be placed in the first hole and the second hole, respectively.
CHIP PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME
A package structure and a method of forming the same are provided. The package structure includes a package substrate and an interposer substrate over the package substrate. The interposer substrate has a first surface facing the package substrate and a second surface opposite the first surface. A first semiconductor device is disposed on the first surface, and a second semiconductor device is disposed on the second surface. Conductive structures are disposed between the interposer substrate and the package substrate. The first semiconductor device is located between the conductive structures. A first side of the first semiconductor device is at a first distance from the most adjacent conductive structure, and a second side of the first semiconductor device is at a second distance from the most adjacent conductive structure. The first side is opposite the second side, and the first distance is greater than the second distance.
CHIP PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME
A package structure and a method of forming the same are provided. The package structure includes a package substrate and an interposer substrate over the package substrate. The interposer substrate has a first surface facing the package substrate and a second surface opposite the first surface. A first semiconductor device is disposed on the first surface, and a second semiconductor device is disposed on the second surface. Conductive structures are disposed between the interposer substrate and the package substrate. The first semiconductor device is located between the conductive structures. A first side of the first semiconductor device is at a first distance from the most adjacent conductive structure, and a second side of the first semiconductor device is at a second distance from the most adjacent conductive structure. The first side is opposite the second side, and the first distance is greater than the second distance.
SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR PACKAGING THE SAME
A semiconductor device package and a method for packaging the same are provided. A semiconductor device package includes a carrier, an electronic component, a buffer layer, a reinforced structure, and an encapsulant. The electronic component is disposed over the carrier and has an active area. The buffer layer is disposed on the active area of the electronic component. The reinforced structure is disposed on the buffer layer. The encapsulant encapsulates the carrier, the electronic component and the reinforced structure.
SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR PACKAGING THE SAME
A semiconductor device package and a method for packaging the same are provided. A semiconductor device package includes a carrier, an electronic component, a buffer layer, a reinforced structure, and an encapsulant. The electronic component is disposed over the carrier and has an active area. The buffer layer is disposed on the active area of the electronic component. The reinforced structure is disposed on the buffer layer. The encapsulant encapsulates the carrier, the electronic component and the reinforced structure.
Anisotropic conductive film and production method of the same
An anisotropic conductive film that can be produced in high productivity and can reduce a short circuit occurrence ratio has a first conductive particle layer in which conductive particles are dispersed at a predetermined depth in a film thickness direction, and a second conductive particle layer in which conductive particles are dispersed at a depth different from that in the first conductive particle layer. In the respective conductive particle layers, the closest distances between the adjacent conductive particles are 2 times or more the average particle diameters of the conductive particles.
Anisotropic conductive film and production method of the same
An anisotropic conductive film that can be produced in high productivity and can reduce a short circuit occurrence ratio has a first conductive particle layer in which conductive particles are dispersed at a predetermined depth in a film thickness direction, and a second conductive particle layer in which conductive particles are dispersed at a depth different from that in the first conductive particle layer. In the respective conductive particle layers, the closest distances between the adjacent conductive particles are 2 times or more the average particle diameters of the conductive particles.
HIGH DENSITY FAN-OUT PACKAGING
Various fan-out devices are disclosed. In one aspect, a semiconductor chip device is provided that includes a redistribution layer structure that has plural conductor structures and plural glass interlevel dielectric layers. A glass encapsulant layer is positioned on the redistribution layer structure. A first semiconductor chip and a second semiconductor chip are positioned in the glass encapsulant layer and electrically connected by at least some of the conductor structures. A cap layer is on the encapsulant layer.
Die with integrated microphone device using through-silicon vias (TSVs)
Embodiments of the present disclosure describe a die with integrated microphone device using through-silicon vias (TSVs) and associated techniques and configurations. In one embodiment, an apparatus includes an apparatus comprising a semiconductor substrate having a first side and a second side disposed opposite to the first side, an interconnect layer formed on the first side of the semiconductor substrate, a through-silicon via (TSV) formed through the semiconductor substrate and configured to route electrical signals between the first side of the semiconductor substrate and the second side of the semiconductor substrate, and a microphone device formed on the second side of the semiconductor substrate and electrically coupled with the TSV. Other embodiments may be described and/or claimed.