Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate that includes a chip region and an edge region around the chip region, and a semiconductor chip on the chip region of the redistribution substrate. The redistribution substrate includes a plurality of dielectric layers that are vertically stacked, a plurality of redistribution patterns on the chip region and in each of the dielectric layers, and a redistribution test pattern on the edge region and at a level the same as a level of at least one of the redistribution patterns.

A mounting apparatus for stacking and mounting two or more semiconductor chips at a plurality of locations on a substrate includes: a first mounting head for forming, at a plurality of locations on the substrate, temporarily stacked bodies in which two or more semiconductor chips are stacked in a temporarily press-attached state; and a second mounting head for forming chip stacked bodies by sequentially finally press-attaching the temporarily stacked bodies formed at the plurality of locations. The second mounting head includes: a press-attaching tool for heating and pressing an upper surface of a target temporarily stacked body to thereby finally press-attach the two or more semiconductor chips configuring the temporarily stacked body altogether; and one or more heat-dissipation tools having a heat-dissipating body which, by coming into contact with an upper surface of another stacked body positioned around the target temporarily stacked body, dissipates heat from the another stacked body.

A flexible three-dimensional electronic device includes a polymer layer having a first side and a second side that is opposite of the first side. A first flexible substrate carrying a first electronic component is arranged on the first side of the polymer layer. A second flexible substrate carries a second electronic component. The second flexible substrate is a flexible silicon substrate arranged on the second side of the polymer layer. An electrically conductive via passes through the polymer layer to electrically connect the first and second electronic components.

A low temperature rapid curing type low elastic conductive adhesive is provided which is useful as a conductive adhesive for component mounting in a field of FHE. The conductive resin composition contains (A) at least two types of urethane acrylate oligomers, (B) a radical polymerizable monomer, (C) a free radical generation curing agent, and (D) conductive particle. In the conductive resin composition, the component (A) preferably contains a high molecular weight urethane acrylate oligomer having a weight average molecular weight of 10,000 or more (A1), and a low molecular weight urethane acrylate oligomer having a weight average molecular weight of 9,999 or less (A2).

The present invention provides a mounting apparatus, including a bonding stage holding a substrate on which a semiconductor chip is arranged; a base stand; a mounting head mounted with a pressing tool that presses the semiconductor chip on the substrate; and a film arranging mechanism provided on the base stand and moving a cover film along the bonding stage to arrange the cover film between the semiconductor chip pressed by the substrate and the pressing tool. The film arranging mechanism includes film guides guiding the cover film and defining a height with respect to the bonding stage; and lifting mechanisms connected to the film guides via springs and lifting and lowering the film guides with respect to the bonding stage.

A light emitting device including at least one LED stack, electrode pads disposed on the LED stack, and cantilever electrodes disposed on the electrode pads, respectively, in which each of the cantilever electrodes has a fixed edge that is fixed to one of the electrode pads and a free standing edge that is spaced apart from the one of the electrode pads.

In an embodiment a composite semiconductor component includes a carrier substrate having a plurality of projecting elements projecting from a first main surface of the carrier substrate, an electrically conductive material electrically conductively connected to a contact region of the carrier substrate and located on at least one of the projecting elements, some of the projecting elements not being covered with the electrically conductive material and a semiconductor chip arranged on the carrier substrate and having at a first surface at least one contact pad electrically connected to the electrically conductive material on at least one element, wherein, at a position at which the contact pad and the electrically conductive material on the projecting element are in each case in contact with one another, the contact pad has a larger lateral extent than the projecting element in each case.

The present disclosure relates to a method for manufacturing a semiconductor package including vacuum-laminating a non-conductive film on a substrate on which a plurality of through silicon vias are provided and bump electrodes are formed, and then performing UV irradiation, wherein an increase in melt viscosity before and after UV irradiation can be adjusted to 30% or less, whereby a bonding can be performed without voids during thermo-compression bonding, and resin-insertion phenomenon between solders can be prevented, fillets can be minimized and reliability can be improved.

The present disclosure relates to a method for manufacturing a semiconductor package including vacuum-laminating a non-conductive film on a substrate on which a plurality of through silicon vias are provided and bump electrodes are formed, and then performing UV irradiation, wherein an increase in melt viscosity before and after UV irradiation can be adjusted to 30% or less, whereby a bonding can be performed without voids during thermo-compression bonding, and resin-insertion phenomenon between solders can be prevented, fillets can be minimized and reliability can be improved.

A multi-die integrated circuit device and a method of fabricating the multi-die integrated circuit device involve a substrate. Two or more dice include components that implement functionality of the multi-die integrated circuit. The components include logic gates. The multi-die integrated circuit device also includes a spacer disposed between the substrate and each of the two or more dice. Each of the two or more dice makes direct electrical contact with the substrate without making direct electrical contact with the spacer through holes in the spacer.