The present disclosure relates to a method for curing a heat-curable material (1) in an embedded curing zone (2) and an assembly resulting from such method. The method comprises providing a heat-conducting strip (3) partially arranged between a component (9) and a substrate (10) that form the embedded curing zone (2) therein between. The heat-conducting strip (3) extends from the embedded curing zone (2) to a radiation-accessible zone (7) that is distanced from the embedded curing zone (2) and at least partially free of the component (9) and the substrate (10). The method further comprises irradiating the heat-conducting strip (3) in the radiation-accessible zone (7) by means of electromagnetic radiation (6). Heat (4a) generated by absorption of the electromagnetic radiation (6) in the heat-conducting strip (3) is conducted from the radiation-accessible zone (7) along a length of the heat-conducting strip (3) to the embedded curing zone (2) to cure the heat-curable material (1) by conducted heat (4b) emanating from the heat-conducting strip (3) into the embedded curing zone (2).

A method of manufacturing a multi-layer wafer is provided. At least one stress compensating polymer layer is applied to at least one of two heterogeneous wafers. The stress compensating polymer layer is low temperature bonded to the other of the two heterogeneous wafers to form a multi-layer wafer pair. Channels are created between die on at least one of the two heterogeneous wafers. The channels are back filled with one of oxide or polymer to create a channel oxide deposition.

Various embodiments of an integrated circuit module and a method of forming such module are disclosed. The module includes a first die having an active substrate, an integrated circuit disposed on a first major surface of the active substrate, and a cavity disposed in a second major surface of the active substrate. The module also includes a second die having a first major surface, a second major surface, and a conductive pad disposed on the second major surface. The second die is disposed at least partially within the cavity of the first die such that the first major surface of the second die faces the cavity of the first die.

Various embodiments of an integrated circuit module and a method of forming such module are disclosed. The module includes a first die having an active substrate, an integrated circuit disposed on a first major surface of the active substrate, and a cavity disposed in a second major surface of the active substrate. The module also includes a second die having a first major surface, a second major surface, and a conductive pad disposed on the second major surface. The second die is disposed at least partially within the cavity of the first die such that the first major surface of the second die faces the cavity of the first die.

A method of manufacturing a multi-layer wafer is provided. The method comprises creating under bump metallization (UMB) pads on each of the two heterogeneous wafers; applying a conductive means above the UMB pads on at least one of the two heterogeneous wafers; and low temperature bonding the two heterogeneous wafers to adhere the UMB pads together via the conductive means. At least one stress compensating polymer layer may be applied to at least one of two heterogeneous wafers. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafer having UMB pads and at least one of the heterogeneous wafers having a stress compensating polymer layer and a conductive means applied above the UMB pads on at least one of the two heterogeneous wafers. The two heterogeneous wafers low temperature bonded together to adhere the UMB pads together via the conductive means.

A semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first semiconductor structure and a second semiconductor structure that are on the first semiconductor chip and spaced apart from each other across the second semiconductor chip, and a resin-containing member between the second semiconductor chip and the first semiconductor structure and between the second semiconductor chip and the second semiconductor structure. The semiconductor package may be fabricated at a wafer level.

A semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first semiconductor structure and a second semiconductor structure that are on the first semiconductor chip and spaced apart from each other across the second semiconductor chip, and a resin-containing member between the second semiconductor chip and the first semiconductor structure and between the second semiconductor chip and the second semiconductor structure. The semiconductor package may be fabricated at a wafer level.

Described herein are printable structures and methods for making, assembling and arranging electronic devices. A number of the methods described herein are useful for assembling electronic devices where one or more device components are embedded in a polymer which is patterned during the embedding process with trenches for electrical interconnects between device components. Some methods described herein are useful for assembling electronic devices by printing methods, such as by dry transfer contact printing methods. Also described herein are GaN light emitting diodes and methods for making and arranging GaN light emitting diodes, for example for display or lighting systems.

A multi-layer wafer and method of manufacturing such wafer are provided. The method includes creating under bump metallization (UMB) pads on each of the two heterogeneous wafers; applying a conductive means above the UMB pads on at least one of the two heterogeneous wafers; and low temperature bonding the two heterogeneous wafers to adhere the UMB pads together via the conductive means. At least one stress compensating polymer layer may be applied to at least one of two heterogeneous wafers. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafer having UMB pads and at least one of the heterogeneous wafers having a stress compensating polymer layer and a conductive means applied above the UMB pads on at least one of the two heterogeneous wafers. The two heterogeneous wafers low temperature bonded together to adhere the UMB pads together via the conductive means.

A die transfer method and a die transfer system thereof are disclosed. The die transfer method includes the following steps: providing a wafer to generate a plurality of dies; transferring a plurality of dies to a surface of a donor substrate to fix the plurality of dies on the surface of the donor substrate by a photoreactive adhesive layer; aligning the donor substrate with a target substrate, wherein the target substrate has a landing site and the position of at least one die corresponds to the position of the landing site; irradiating the donor substrate with a radiation beam to cause the photoreactive adhesive layer to drop the at least one die, such that the at least one die is transferred onto the landing site of the target substrate; and fixing the at least one die at the landing site.