Patent classifications
H01L2224/83871
Adhesive bonding composition and electronic components prepared from the same
A curable resin or adhesive composition includes at least one monomer, a photoinitiator capable of initiating polymerization of the monomer when exposed to light, and at least one energy converting material, preferably a phosphor, capable of producing light when exposed to radiation (typically X-rays). The material is particularly suitable for bonding components at ambient temperature in situations where the bond joint is not accessible to an external light source. An associated method includes: placing a polymerizable adhesive composition, including a photoinitiator and energy converting material, such as a down-converting phosphor, in contact with at least two components to be bonded to form an assembly; and, irradiating the assembly with radiation at a first wavelength, capable of conversion (down-conversion by the phosphor) to a second wavelength capable of activating the photoinitiator, to prepare items such as inkjet cartridges, wafer-to-wafer assemblies, semiconductors, integrated circuits, and the like.
Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same
Semiconductor assemblies including thermal management configurations for reducing heat transfer between overlapping devices and associated systems and methods are disclosed herein. A semiconductor assembly may comprise a first device and a second device with a thermally conductive layer, a thermal-insulator interposer, or a combination thereof disposed between the first and second devices. The thermally conductive layer and/or the thermal-insulator interposer may be configured to reduce heat transfer between the first and second devices.
Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same
Semiconductor assemblies including thermal management configurations for reducing heat transfer between overlapping devices and associated systems and methods are disclosed herein. A semiconductor assembly may comprise a first device and a second device with a thermally conductive layer, a thermal-insulator interposer, or a combination thereof disposed between the first and second devices. The thermally conductive layer and/or the thermal-insulator interposer may be configured to reduce heat transfer between the first and second devices.
INTEGRATED CIRCUIT PACKAGES TO MINIMIZE STRESS ON A SEMICONDUCTOR DIE
An integrated circuit package can contain a semiconductor die and provide electrical connections between the semiconductor die and additional electronic components. The integrated circuit package can reduce stress placed on the semiconductor die due to movement of the integrated circuit package due to, for example, temperature changes and/or moisture levels. The integrated circuit package can at least partially mechanically isolate the semiconductor die from the integrated circuit package.
INTEGRATED CIRCUIT PACKAGES TO MINIMIZE STRESS ON A SEMICONDUCTOR DIE
An integrated circuit package can contain a semiconductor die and provide electrical connections between the semiconductor die and additional electronic components. The integrated circuit package can reduce stress placed on the semiconductor die due to movement of the integrated circuit package due to, for example, temperature changes and/or moisture levels. The integrated circuit package can at least partially mechanically isolate the semiconductor die from the integrated circuit package.
ELECTRONIC DEVICE AND METHOD OF TRANSFERRING ELECTRONIC ELEMENT USING STAMPING AND MAGNETIC FIELD ALIGNMENT
The present disclosure provides a method of transferring an electronic element using a stamping and magnetic field alignment technology and an electronic device including an electronic element transferred using the method. In the present disclosure, a polymer may be simultaneously coated on a plurality of electronic elements using the stamping process, and the polymer may be actively coated on the electronic elements without restrictions on process parameters such as size and spacing of the electronic elements. Moreover, the self-aligned ferromagnetic particles have an anisotropic current flow through which current flows only in the aligned direction. Therefore, the current may flow only vertically between the electronic element and the electrode, and there is no electrical short circuit between a peripheral LED element and the electrode.
Method for manufacturing semiconductor structure
A method includes followings operations. A substrate including a first surface and a second surface is provided. The substrate and a transparent film are heated to attach the transparent film on the first surface. A first coefficient of a thermal expansion (CTE) mismatch is between the substrate and the transparent film. The substrate and the transparent film are cooled. A polymeric material is disposed on the second surface. A second CTE mismatch is between the substrate and the polymeric material. The second CTE mismatch is counteracted by the first CTE mismatch.
ELECTRONIC DEVICE AND METHOD OF TRANSFERRING ELECTRONIC ELEMENT USING STAMPING AND MAGNETIC FIELD ALIGNMENT
The present disclosure provides a method of transferring an electronic element using a stamping and magnetic field alignment technology and an electronic device including an electronic element transferred using the method. In the present disclosure, a polymer may be simultaneously coated on a plurality of electronic elements using the stamping process, and the polymer may be actively coated on the electronic elements without restrictions on process parameters such as size and spacing of the electronic elements. Moreover, the self-aligned ferromagnetic particles have an anisotropic current flow through which current flows only in the aligned direction. Therefore, the current may flow only vertically between the electronic element and the electrode, and there is no electrical short circuit between a peripheral LED element and the electrode.
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
A semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first semiconductor structure and a second semiconductor structure that are on the first semiconductor chip and spaced apart from each other across the second semiconductor chip, and a resin-containing member between the second semiconductor chip and the first semiconductor structure and between the second semiconductor chip and the second semiconductor structure. The semiconductor package may be fabricated at a wafer level.
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
A semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first semiconductor structure and a second semiconductor structure that are on the first semiconductor chip and spaced apart from each other across the second semiconductor chip, and a resin-containing member between the second semiconductor chip and the first semiconductor structure and between the second semiconductor chip and the second semiconductor structure. The semiconductor package may be fabricated at a wafer level.