A bonding film for bonding a semiconductor element and a substrate. The bonding film has an electroconductive bonding layer formed by molding an electroconductive paste including metal fine particles (P) into a film form, and a tack layer having tackiness and laminated on the electroconductive bonding layer. The tack layer includes 0.1% to 1.0% by mass of metal fine particles (M) with respect to the metal fine particles (P) in the electroconductive bonding layer, and the metal fine particles (M) have a melting point of 250° C. or lower.

A method of forming a wire loop in connection with a semiconductor package is provided. The method includes the steps of: (1) providing package data related to the semiconductor package to a wire bonding machine; (2) providing at least one looping control value related to a desired wire loop to the wire bonding machine, the at least one looping control value including at least a loop height value related to the desired wire loop; (3) deriving looping parameters, using an algorithm, for forming the desired wire loop; (4) forming a first wire loop on the wire bonding machine using the looping parameters derived in step (3); (5) measuring actual looping control values of the first wire loop formed in step (4) corresponding to the at least one looping control value; and (6) comparing the actual looping control values measured in step (5) to the at least one looping control value provided in step (2).

A method of forming a wire loop in connection with a semiconductor package is provided. The method includes the steps of: (1) providing package data related to the semiconductor package to a wire bonding machine; (2) providing at least one looping control value related to a desired wire loop to the wire bonding machine, the at least one looping control value including at least a loop height value related to the desired wire loop; (3) deriving looping parameters, using an algorithm, for forming the desired wire loop; (4) forming a first wire loop on the wire bonding machine using the looping parameters derived in step (3); (5) measuring actual looping control values of the first wire loop formed in step (4) corresponding to the at least one looping control value; and (6) comparing the actual looping control values measured in step (5) to the at least one looping control value provided in step (2).

Provided is a wire bonding method capable of suppressing the occurrence of wire breakage. One aspect of the present invention provides a wire bonding method for bringing a capillary and a wire 1 inserted through the capillary into pressure contact with a second bonding point 16 of a lead placed on an XY stage to bond the wire to the lead, including moving the XY stage in a state in which the capillary is in pressure contact with the lead to move the capillary along a movement locus including a plurality of arc portions.

A wire bonding method includes bonding a tip of a wire provided through a clamp and a capillary onto a bonding pad of a chip, moving the capillary to a connection pad of a substrate corresponding to the bonding pad, bonding the wire to the connection pad to form a bonding wire connecting the bonding pad to the connection pad, before the capillary is raised from the connection pad, applying a electrical signal to the wire to detect whether the wire and the connection pad are in contact with each other, changing a state of the clamp to a closed state when the wire is not in contact with the connection pad and maintaining the state of the clamp in an open state when the wire is in contact with the connection pad, and raising the capillary from the connection pad while maintaining the state of the clamp.

A multi-sided cooling semiconductor package includes a first substrate, a second substrate, semiconductor chips disposed between the first substrate and the second substrate, and first metal preforms. The first substrate includes a upper metal layer, a lower metal layer, and a dielectric plate between the upper metal layer and the lower metal layer. The second substrate also includes a upper metal layer, a lower metal layer, and a dielectric plate between the upper metal layer and the lower metal layer. The first metal preforms are disposed between the first substrate and the semiconductor chips and between the second substrate and the semiconductor chips. A first part of the first metal preforms is in direct contact with the upper metal layer of the first substrate, and a second part of the first metal preforms is in direct contact with the lower metal layer of the second substrate.

A bonding wire for connecting a first pad to a second pad is provided. The bonding wire includes a ball part bonded to the first pad, a neck part formed on the ball part, and a wire part extending from the neck part to the second pad. Less than an entire portion of a top surface of the neck part is covered by the wire part, and the wire part is in contact with the neck part, the ball part, and the first pad.

A bonding wire for connecting a first pad to a second pad is provided. The bonding wire includes a ball part bonded to the first pad, a neck part formed on the ball part, and a wire part extending from the neck part to the second pad. Less than an entire portion of a top surface of the neck part is covered by the wire part, and the wire part is in contact with the neck part, the ball part, and the first pad.

A Pd-coated Cu bonding wire of an embodiment contains Pd of 1.0 to 4.0 mass %, and a S group element of 50 mass ppm or less in total (S of 5.0 to 12.0 mass ppm, Se of 5.0 to 20.0 mass ppm, or Te of 15.0 to 50 mass ppm). At a crystal plane of a cross section of the wire, a <100> orientation ratio is 15% or more, and a <111> orientation ratio is 50% or less. When a free air ball is formed on the wire and a tip portion is analyzed, a Pd-concentrated region is observed on the surface thereof.

The present disclosure provides a package structure, including a mounting pad having a mounting surface, a semiconductor chip disposed on the mounting surface of the mounting pad, wherein the semiconductor chip includes a first surface, a second surface opposite to the first surface and facing the mounting surface, and a third surface connecting the first surface and the second surface, a first magnetic field shielding, including a first portion proximal to the third surface of the semiconductor chip, wherein the first portion has a first height calculated from the mounting surface to a top surface, and a second portion distal to the semiconductor chip, has a second height calculated from the mounting surface to a position at a surface facing away from the mounting surface, wherein the second height is less than the first height, wherein the second portion has an inclined sidewall.