An electronic module has a first substrate 11, a first conductor layer 12 that is provided on one side of the first substrate 11, a first electronic element 13 that is provided on one side of the first conductor layer 12, a second electronic element 23 that is provided on one side of the first electronic element 23, and a second connecting body 70 that has a second head part 71 provided on one side of the second electronic element 23 and an extending part 75 extending from the second head part 71 to the other side and abutting against the first substrate 11 or the first conductor layer 12.

An apparatus comprising: a die stack comprising at least one die pair, the at least one die pair having a first die over a second die, the first die and the second die both having a first surface and a second surface, the second surface of the first die over the first surface of the second die; and an adhesive film between the first die and the second die of the at least one die pair; wherein the adhesive film comprises an insulating layer and a conductive layer, the insulating layer adhering to the second surface of the first die and the conductive layer adhering to the first surface of the second die.

A semiconductor package includes a metallic pad and leads, a semiconductor die attached to the metallic pad, the semiconductor die including an active side with bond pads opposite the metallic pad, a wire bond extending from a respective bond pad of the semiconductor die to a respective lead of the leads, a heat spreader over the active side of the semiconductor die with a gap separating the active side of the semiconductor die from the heat spreader, an electrically insulating material within the gap and in contact with the active side of the semiconductor die and the heat spreader; and mold compound covering the semiconductor die and the wire bond, and partially covering the metallic pad and the heat spreader, with the metallic pad exposed on a first outer surface of the semiconductor package and with the heat spreader exposed on a second outer surface of the semiconductor package.

A package includes a first chip stack. The first chip stack includes a first chip including first bonding structures, a second chip including second bonding structures facing the first bonding structures and bonded to the first bonding structures, and a first electrical contact on the second chip. At least a portion of the first electrical contact does not overlap with the first chip in a plan view.

The present disclosure provides a semiconductor package. The semiconductor package includes a carrier member, a plurality of inductors and a memory chip. The carrier member includes a first surface, a second surface and a centrally-located opening. The carrier member also includes a plurality of conductive pads on the second surface proximal to the opening. The memory chip is attached to the carrier member in a face-down manner. The memory chip includes a plurality of bidirectional and unidirectional signal-transmission pins electrically coupled to the inductors. The memory chip also includes a plurality of bonding pads. A plurality of bonding wires, passing through the opening, electrically connect the bonding pads on the memory chip to the conductive pads on the carrier member. A first insulative structure substantially encapsulates the memory chip and the inductors. A plurality of solder balls are attached to the second surface of the carrier member.

The present disclosure provides a semiconductor package. The semiconductor package includes a carrier member, a plurality of inductors and a memory chip. The carrier member includes a first surface, a second surface and a centrally-located opening. The carrier member also includes a plurality of conductive pads on the second surface proximal to the opening. The memory chip is attached to the carrier member in a face-down manner. The memory chip includes a plurality of bidirectional and unidirectional signal-transmission pins electrically coupled to the inductors. The memory chip also includes a plurality of bonding pads. A plurality of bonding wires, passing through the opening, electrically connect the bonding pads on the memory chip to the conductive pads on the carrier member. A first insulative structure substantially encapsulates the memory chip and the inductors. A plurality of solder balls are attached to the second surface of the carrier member.

A microelectronic package may be fabricated having at least one microelectronic die attached to a microelectronic substrate, wherein the microelectronic substrate includes at least one notch formed in at least one side thereof. The microelectronic dice may be attached to a first surface of the microelectronic substrate and in electronic communication with a bond pad on a second surface of the microelectronic substrate with a bond wire which extends through the notch in the microelectronic substrate.

Structures and methods are disclosed for shielding magnetically sensitive components. One structure includes a substrate, a bottom shield deposited on the substrate, a magnetoresistive semiconductor device having a first surface and a second surface opposing the first surface, the first surface of the magnetoresistive semiconductor device deposited on the bottom shield, a top shield deposited on the second surface of the magnetoresistive semiconductor device, the top shield having a window for accessing the magnetoresistive semiconductor device, and a plurality of interconnects that connect the magnetoresistive semiconductor device to a plurality of conductive elements.

An image sensor package according to an embodiment of the present technology includes: a solid-state image sensor; a transparent substrate; and a package substrate. The solid-state image sensor has a light-receiving surface including a light-reception unit and a first terminal unit, and a rear surface opposite to the light-receiving surface. The transparent substrate faces the light-receiving surface. The package substrate includes a frame portion, a second terminal unit, and a supporting body. The frame portion has a joint surface to be joined to the transparent substrate and includes a housing portion housing the solid-state image sensor. The second terminal unit is to be wire-bonded to the first terminal unit, the second terminal unit being provided in the frame portion. The supporting body is provided in a peripheral portion of the light-receiving surface or at a center portion of the rear surface and partially supports the light-receiving surface or the rear surface.

An integrated semiconductor device and a method for manufacturing the integrated semiconductor device are disclosed. In an embodiment an integrated semiconductor device includes a supporting substrate having a first substrate face and a second substrate face opposite to the first substrate face, a semiconductor die having a first die face coupled to the first substrate face of the supporting substrate, the first die face including first die contact pads, wherein the supporting substrate has at least one through opening, wherein the first die contact pads are arranged facing the through opening, and wherein the supporting substrate comprises first substrate contact pads connected by first bonding wires to the respective first die contact pads through the through opening.