An apparatus comprising: a die stack comprising at least one die pair, the at least one die pair having a first die over a second die, the first die and the second die both having a first surface and a second surface, the second surface of the first die over the first surface of the second die; and an adhesive film between the first die and the second die of the at least one die pair; wherein the adhesive film comprises an insulating layer and a conductive layer, the insulating layer adhering to the second surface of the first die and the conductive layer adhering to the first surface of the second die.

According to one embodiment, a magnetic memory device includes a magnetic memory chip having a magnetoresistive element, a magnetic layer having first and second portions spacing out each other, the first portion covering a first main surface of the magnetic memory chip, the second portion covering a second main surface facing the first main surface of the magnetic memory chip, a circuit board on which the magnetic layer is mounted, and a bonding wire connecting between the magnetic memory chip and the circuit board in a first direction parallel to the first and second main surfaces.

Aspects of the disclosure provide an integrated circuit (IC) package. The IC package includes a package substrate, one or more IC chips, a marking plate and a plastic structure. The one or more IC chips are interconnected with the package substrate. The marking plate has a first major surface and a second major surface. The marking plate is stacked on the one or more IC chips with the first major surface facing the one or more IC chips. The plastic structure is configured to encapsulate the one or more IC chips and the marking plate with the second major surface of the marking plate being a portion of an outer surface of the IC package.

A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a plurality of first chip connection units to connect the first package substrate to the first semiconductor chip, an interposer on the first semiconductor chip, the interposer having a width greater than a width of the first semiconductor chip in a direction parallel to an upper surface of the first package substrate, and an upper filling layer including a center portion and an outer portion, the center portion being between the first semiconductor chip and the interposer, and the outer portion surrounding the center portion and having a thickness greater than a thickness of the center portion in a direction perpendicular to the upper surface of the first package substrate.

A chip carrier which comprises a thermally conductive and electrically insulating sheet, a first electrically conductive structure on a first main surface of the sheet, and a second electrically conductive structure on a second main surface of the sheet, wherein the first electrically conductive structure and the second electrically conductive structure extend beyond a lateral edge of the sheet.

A bonding wire for connecting a first pad to a second pad is provided. The bonding wire includes a ball part bonded to the first pad, a neck part formed on the ball part, and a wire part extending from the neck part to the second pad. Less than an entire portion of a top surface of the neck part is covered by the wire part, and the wire part is in contact with the neck part, the ball part, and the first pad.

A semiconductor memory includes a substrate, a memory controller, a plurality of memory modules, and a cover layer. The memory controller is provided on an upper surface of the substrate. Each of the memory modules partially covers an upper surface of the memory controller and the upper surface of the substrate through at least an adhesive layer. The cover layer is on the upper surface of the substrate and encloses the memory controller and the plurality of memory modules between the substrate and the cover layer.

A semiconductor package is provided. The semiconductor package includes: a mounting substrate including at least one bonding pad; a first semiconductor chip disposed on the mounting substrate, and including a first protrusion on one side of the first semiconductor chip; a first spacer ball electrically connected to the first semiconductor chip; a first bump ball electrically connected to the first spacer ball; and a first wire which electrically connects the first bump ball and the bonding pad without contacting the first protrusion, wherein the first wire includes a first portion extending in a direction away from the bonding pad, and a second portion extending in a direction approaching the bonding pad.

A semiconductor package including a package base substrate; at least one semiconductor chip on the package base substrate; a heat sink attached on the at least one semiconductor chip, the heat sink including a base and a plurality of protrusion patterns on a top of the base; and a molding covering a top of the package base substrate, a side surface of the at least one semiconductor chip, and a side surface of the heat sink without covering a top of the heat sink.

A semiconductor package includes: a package substrate; a semiconductor chip disposed on the package substrate; a transparent substrate disposed on the semiconductor chip; and an adhesive layer that is disposed between the semiconductor chip and the transparent substrate. The adhesive layer is configured to block light. The transparent substrate includes: a first lower side that faces the semiconductor chip, a second lower side that faces the semiconductor chip and that is disposed above the first lower side, and a first inner side wall that connects the first lower side and the second lower side, and the adhesive layer is in contact with the second lower side and the first inner side wall.