A multi-chip package includes: a first semiconductor integrated-circuit (IC) chip; a second semiconductor integrated-circuit (IC) chip over and bonded to the first semiconductor integrated-circuit (IC) chip; a plurality of first metal posts over and coupling to the first semiconductor integrated-circuit (IC) chip, wherein the plurality of first metal posts are in a space beyond and extending from a sidewall of the second semiconductor integrated-circuit (IC) chip; and a first polymer layer over the first semiconductor integrated-circuit (IC) chip and in the space, wherein the plurality of first metal posts are in the first polymer layer, wherein a top surface of the first polymer layer, a top surface of the second semiconductor integrated-circuit (IC) chip and a top surface of each of the plurality of first metal posts are coplanar.

A method of forming a package comprises assembling at least one chip layer over a carrier substrate, the at least one chip layer including chip couplers and chips, each of the chips having a front side facing the carrier substrate and chip contacts formed on the front side, the couplers including first chip couplers, each of the first chip couplers having an upper side facing away from the carrier substrate and first bumps formed on the upper side. The method further comprises encapsulating the at least one chip layer to form a molded package structure, thinning the molded package structure to expose the first bumps, forming a metal layer on a side of the molded package structure where the first bumps are exposed, removing the carrier to expose another side of the molded package structure, and forming a redistribution layer and second bumps on the molded package structure.

A semiconductor packaging method, a semiconductor assembly and an electronic device are disclosed herein. The semiconductor packaging method comprises providing at least one semiconductor device and a first carrier board. The at least one semiconductor device has a passive surface with first alignment solder parts formed thereon, and the first carrier board has a plurality of corresponding second alignment solder parts formed thereon. The method further comprises forming alignment solder joints by aligning and soldering the first alignment solder parts to respective ones of the second alignment solder parts; removing the first carrier board after attaching a second carrier board to the active surface of the at least one semiconductor device; forming a molded package body on one side of the second carrier board to encapsulate the at least one semiconductor device; and removing the second carrier board to expose the connecting terminals.

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

Disclosed herein are microelectronic structures including glass cores, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a glass core having through-glass vias (TGVs) therein; a metallization region at a first face of the glass core, wherein a conductive pathway in the first metallization region is conductively coupled to at least one of the TGVs; a bridge component in the metallization region; a first conductive contact at a face of the metallization region, wherein the first conductive contact is conductively coupled to the conductive pathway; and a second conductive contact at the face of the metallization region, wherein the second conductive contact is conductively coupled to the bridge component.

An apparatus is provided which comprises: a cavity made in a substrate of a printed circuit board (PCB); a plurality of solder balls embedded in the cavity; and a horizontal trace within the substrate, wherein the horizontal trace is partially directly under the plurality of solder balls and is coupled to the plurality of solder balls and another trace or via in the substrate such that a substrate region under the plurality of solder balls is independent of a stop layer under the cavity.

A package structure includes at least one semiconductor die, an insulating encapsulant, an isolation layer and a redistribution layer. The at least one first semiconductor die has a semiconductor substrate and a conductive post disposed on the semiconductor substrate. The insulating encapsulant is partially encapsulating the first semiconductor die, wherein the conductive post has a first portion surrounded by the insulating encapsulant and a second portion that protrudes out from the insulating encapsulant. The isolation layer is disposed on the insulating encapsulant and surrounding the second portion of the conductive post. The redistribution layer is disposed on the first semiconductor die and the isolation layer, wherein the redistribution layer is electrically connected to the conductive post of the first semiconductor die.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.