Disclosed is a semiconductor package including: a redistribution substrate; at least one passive device in the redistribution substrate, the passive device including a first terminal and a second terminal; and a semiconductor chip on a top surface of the redistribution substrate, the semiconductor chip vertically overlapping at least a portion of the passive device, wherein the redistribution substrate includes: a dielectric layer in contact with a first lateral surface, a second lateral surface opposite to the first lateral surface, and a bottom surface of the passive device; a lower conductive pattern on the first terminal; a lower seed pattern provided between the first terminal and the conductive pattern, and directly connected to the first terminal; a first upper conductive pattern on the second terminal and a first upper seed pattern provided between the second terminal and the first upper conductive pattern, and directly connected to the second terminal

A method includes bonding a first device die with a second device die. The second device die is over the first device die. A passive device is formed in a combined structure including the first and the second device dies. The passive device includes a first and a second end. A gap-filling material is formed over the first device die, with the gap-filling material including portions on opposite sides of the second device die. The method further includes performing a planarization to reveal the second device die, with a remaining portion of the gap-filling material forming an isolation region, forming a first and a second through-vias penetrating through the isolation region to electrically couple to the first device die, and forming a first and a second electrical connectors electrically coupling to the first end and the second end of the passive device.

A manufacturing method of a semiconductor package includes a groove forming step of cutting a semiconductor package substrate from an upper surface side along division lines in a cut-in-depth range of at least such a depth as to cause a ground line included in a wiring substrate to be exposed in a processing groove to such a depth that the semiconductor package substrate is not fully cut with a first cutting blade, thereby forming the processing groove having a first width at least on an upper surface of a sealing material, a shielding layer forming step of forming a shielding layer on a side surface of the processing groove, a bottom surface of the processing groove, and the upper surface of the sealing material with a conductive material from an upper side of the sealing material, and a dividing step of, cutting the semiconductor package substrate into individual semiconductor packages.

A semiconductor package assembly is provided. The semiconductor package assembly includes a base, a first system-on-chip (SOC) die, a conductive routing and a first shielding film. The first SOC die is disposed on the base. The first SOC die has a front surface and a back surface. The first SOC die includes a first inductor close to the front surface. The conductive routing is disposed on the back surface of the first SOC die. The first shielding film is disposed between the first SOC die and the conductive routing. The first shielding film covers the back surface of the first SOC die and fully overlaps the first inductor.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure and a first connecting structure, wherein the first connecting structure includes a first connecting insulating layer positioned on the first semiconductor structure, two first conductive layers positioned in the first connecting insulating layer, and a first porous layer positioned between the two first conductive layers. A porosity of the first porous layer is between about 25% and about 100%.

In one embodiment, a multi-die complex includes a mold material, first and second integrated circuit dies within the mold material, and one or more metal layers within the mold material. One or more passive electrical components, e.g., an inductor, a capacitor, or RF shielding, are formed at least partially within the metal layers.

A semiconductor package is described herein with electromagnetic shielding using metal layers and vias. In one example, the package includes a silicon substrate having a front side and a back side, the front side including active circuitry and an array of contacts to attach to a substrate, a metallization layer over the back side of the die to shield active circuitry from interference through the back side, and a plurality of through-silicon vias coupled to the back side metallization at one end and to front side lands of the array of lands at the other end to shield active circuitry from interference through the sides of the die.

The present disclosure is directed to improving EMI shielding to provide more reliable semiconductor packages. The semiconductor package may be, for example, a lead frame including one or multiple dies attached thereto. The semiconductor package may include only wire bonds or a combination of clip bonds and wire bonds. An integrated shielding structure may be disposed in between the package substrate and the encapsulant to shield internal and/or external EMI. For example, a top surface of the integrated shield structure is exposed.

The invention provides a package structure, comprising: a substrate disposed with a solid grounded copper layer; at least two radio frequency chip modules disposed on the substrate; a plastic encapsulation disposed on the substrate, covered on a surface of the substrate, and coating the at least two radio frequency chip modules therein; a groove located between the adjacent two radio frequency chip modules, and penetrating an upper surface and a lower surface of the plastic encapsulation; a solder filling body filled in the groove, wherein an upper surface of the solder filling body is flushed with the upper surface of the plastic encapsulation; and a shielding layer covered on the upper surface and lateral surfaces of the plastic encapsulation, an upper surface of the solder filling body and lateral surfaces of the substrate; wherein a position of the solid grounded copper layer corresponds to a position of the groove, and makes contact with the solder filling body in the groove.

A semiconductor package includes at least one semiconductor device mounted on a first substrate, a thermosetting resin layer on the at least one semiconductor device, the thermosetting resin layer including an irreversible thermochromic pigment, a metal plate on the thermosetting resin layer, and a molding member surrounding the at least one semiconductor device at least in a lateral direction and being in contact with the thermosetting resin layer.