A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

Disclosed is a semiconductor package with Pillar-Top-Interconnection (PTI) configuration, comprising a redistribution layer (RDL) formed on a carrier plane, a plurality of metal pillars disposed on the RDL, a chip bonded onto the RDL, and a molding core. The molding core is formed on the carrier plane and has a bottom surface defined by the carrier plane so that the RDL is embedded inside the molding core. The package thickness of the molding core is greater than the chip-bonding height of the chip so that the chip is completely embedded inside the molding core. The metal pillars are encapsulated at the peripheries of the molding core with a plurality of pillar top portions exposed from the molding core. The exposed pillar top portions are reentrant from a top surface of the molding core and uneven. Accordingly, it realizes the effects of ultra-thin and smaller footprint POP stacked assembly with fine pitch vertically electrical connections in POP structure. Also, it is possible to achieve zero spacing between POP stacked assembly.

A device includes a driver circuit, a first semiconductor chip monolithically integrated with the driver circuit in a first semiconductor material, and a second semiconductor chip integrated in a second semiconductor material. The second semiconductor material is a compound semiconductor.

A microelectronic unit can include a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at the front surface and an inner surface located below the front surface of the carrier structure. The microelectronic unit can also include a microelectronic element having a top surface adjacent the inner surface, a bottom surface remote from the top surface, and a plurality of contacts at the top surface. The microelectronic unit can also include terminals electrically connected with the contacts of the microelectronic element. The terminals can be electrically insulated from the carrier structure. The microelectronic unit can also include a dielectric region contacting at least the bottom surface of the microelectronic element. The dielectric region can define a planar surface located coplanar with or above the front surface of the carrier structure.

Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an L shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a C shape and include a tiered portion that projects towards the lateral side of the second casing.

A process for manufacturing a surface-mount electronic device includes forming a plurality of preliminary contact regions of a sinterable material on a supporting structure, the supporting structure being of a soluble type. A chip including a semiconductor body is mechanically coupled to the supporting structure. The sinterable material is sintered such that each preliminary contact region forms a corresponding sintered preliminary contact, and the chip and the plurality of preliminary contact regions are coated with a dielectric coating region, and the supporting structure is removed using a jet of liquid.

An electronic device comprising a package comprising an encapsulated electronic chip, at least one at least partially exposed electrically conductive carrier lead for mounting the package on and electrically connecting the electronic chip to a carrier, and at least one at least partially exposed electrically conductive connection lead, and an electronic member stacked with the package so as to be mounted on and electrically connected to the package by the at least one connection lead.

An assembly includes a plurality of stacked encapsulated microelectronic packages, each package including a microelectronic element having a front surface with a plurality of chip contacts at the front surface and edge surfaces extending away from the front surface. An encapsulation region of each package contacts at least one edge surface and extends away therefrom to a remote surface of the package. The package contacts of each package are disposed at a single one of the remote surfaces, the package contacts facing and coupled with corresponding contacts at a surface of a substrate nonparallel with the front surfaces of the microelectronic elements therein.

A microelectronic unit can include a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at the front surface and an inner surface located below the front surface of the carrier structure. The microelectronic unit can also include a microelectronic element having a top surface adjacent the inner surface, a bottom surface remote from the top surface, and a plurality of contacts at the top surface. The microelectronic unit can also include terminals electrically connected with the contacts of the microelectronic element. The terminals can be electrically insulated from the carrier structure. The microelectronic unit can also include a dielectric region contacting at least the bottom surface of the microelectronic element. The dielectric region can define a planar surface located coplanar with or above the front surface of the carrier structure.

A process for manufacturing at least one 3D electronic module each comprises a stack of electronic packages and/or printed wiring boards, wherein a stack is placed on an electrically interconnecting system comprising metal leads each having two ends. The process comprises the following steps: starting with a lead frame that comprises metal leads, folding by about 180 the leads in order to obtain what is referred to as an internal frame portion including the folded ends, which are intended to be molded, the other portion, which is what is referred to as an external portion, including the unfolded exterior ends, the two ends of each lead being intended to emerge from the 3D module on a given face cut along Z; depositing on the leads a metal coating; placing the external portion of the frame between two, an upper and lower, protective elements while leaving the internal portion free, and placing the frame and the protective elements on a carrier; placing each stack equipped each with exterior interconnection tabs so as to superpose the exterior tabs on the internal portion; molding, in a resin, the stack, the exterior tabs and the internal portion and thereby partially covering the upper protective element; cutting the resin and thereby leaving flush conductive sections of the exterior tabs and of the ends of the leads and removing the resin from the upper protective element; metallizing the cut faces; removing the carrier; and removing the protective elements in order to expose the leads of the external portion.