Patent classifications
H03F1/0238
Amplifier for driving a capacitive load
It is disclosed an amplifier for driving a capacitive load, comprising an input terminal adapted to receive an input voltage signal, an output terminal adapted to drive the capacitive load, a linear amplification stage, switching amplification stage, a capacitor, a first switch and a measurement and control circuit. The measurement and control circuit is configured to: measure the value of the current generated at the output from the linear amplification stage and generate a driving voltage signal of the switching amplification stage; generate the first switching signal to open the first switch and generate an enabling signal to enable the operation of at least part of the switching amplification stage; generate the first switching signal to close the first switch and generate the enabling signal to disable the operation of the switching amplification stage; generate the first switching signal to open the first switch.
POWER MANAGEMENT CIRCUIT OPERABLE WITH GROUP DELAY
A power management circuit operable with group delay is provided. The power management circuit includes a transceiver circuit configured to generate a digital target voltage and digitally delay the digital target voltage to generate multiple delayed digital target voltages. Accordingly, the transceiver circuit can generate a windowed digital target voltage in multiple delay tolerance windows based on the delayed digital target voltages. Since the windowed digital target voltage can tolerate a certain amount of group delay in each of the group delay tolerance windows, an envelope tracking (ET) voltage generated based on an analog version of the windowed digital target voltage can therefore tolerate the group delay in each of the group delay tolerance windows as well. As a result, it is possible to avoid distortion in the ET voltage to help improve performance of the power management circuit.
Apparatus and methods for power amplifiers with positive envelope feedback
Apparatus and methods for power amplifiers with positive envelope feedback are provided herein. In certain implementations, a power amplifier system includes a power amplification stage that amplifies a radio frequency signal, at least one envelope detector that generates one or more detection signals indicating an output signal envelope of the power amplification stage, and a wideband feedback circuit that provides positive envelope feedback to a bias of the power amplification stage based on the one or more detection signals. The power amplifier system further includes a supply modulator that controls a voltage level of a supply voltage of the power amplification stage based on the one or more detection signals such that the supply voltage is modulated with the output signal envelope through positive envelope feedback.
POWER AMPLIFIER WITH PROTECTION LOOP
A power amplifier includes an over-current protection loop and/or an over-voltage protection loop to assist in preventing operation outside a safe operation zone. In a further exemplary aspect, triggering of the over-current protection loop adjusts a threshold voltage for the over-voltage protection loop. In further exemplary aspects, the over-current protection loop may adjust not only a bias regulator, but also provide an auxiliary control signal that further limits signals reaching the power amplifier. In still further exemplary aspects, the over-voltage protection loop may operate independently of the over-current protection current loop or the over-voltage protection loop contribute to an over-current protection signal.
POWER AMPLIFIER WITH PROTECTION LOOPS
A power amplifier includes an over-current protection loop and/or an over-voltage protection loop to assist in preventing operation outside a safe operation zone. In a further exemplary aspect, triggering of the over-current protection loop adjusts a threshold voltage for the over-voltage protection loop. In further exemplary aspects, the over-current protection loop may adjust not only a bias regulator, but also provide an auxiliary control signal that further limits signals reaching the power amplifier. In still further exemplary aspects, the over-voltage protection loop may operate independently of the over-current protection current loop or the over-voltage protection loop contribute to an over-current protection signal.
LOW-NOISE POWER SOURCES FOR IMAGING SYSTEMS
Power supplies for electronic devices (e.g. medical imaging devices) are disclosed herein. In one embodiment, a switched mode power supply is minimized in size and weight while maintaining efficiency and an artifact-free image using power supply design techniques tailored to increasing the power conversion frequency to be above the desired receive band of an ultrasound imaging system. In another embodiment, a switched mode power supply is minimized in size and weight while maintaining efficiency and an artifact-free image using power supply design techniques tailored to increasing the power conversion frequency to be just below the desired receive band of an ultrasound imaging system causing the third harmonic and possibly the second harmonic to fall just above the desired receive band.
ENVELOPE TRACKING WITH DYNAMICALLY CONFIGURABLE ERROR AMPLIFIER
Apparatus and methods for power amplifier envelope tracking systems with automatic control of a slew rate and a mode of an error amplifier of the envelope tracking system. The envelope tracker can include a signal bandwidth detection circuit that processes the envelope signal to generate a detected bandwidth signal, and a control circuit that controls the slew rate of the error amplifier based on the detected signal bandwidth.
Envelope tracking radio frequency front-end circuit
An envelope tracking (ET) radio frequency (RF) front-end circuit is provided. The ET RF front-end circuit includes an ET integrated circuit(s) (ETIC(s)), a local transceiver circuit, a target voltage circuit(s), and a number of power amplifiers. The local transceiver circuit receives an input signal(s) from a coupled baseband transceiver and generates a number of RF signals. The target voltage circuit(s) generates a time-variant ET target voltage(s) based on the input signal(s). The ETIC(s) generates multiple ET voltages based on the time-variant ET target voltage(s). The power amplifiers amplify the RF signals based on the ET voltages. Given that the time-variant ET target voltage(s) is generated inside the self-contained ET RF front-end circuit, it is possible to reduce distortion in the time-variant ET target voltage(s), thus helping to improve operating efficiency of the power amplifiers, especially when the RF signals are modulated with a higher modulation bandwidth (e.g., ≥200 MHz).
Load insensitive power detection
A load-insensitive power amplifier power detector that excludes the use of couplers is disclosed. The load-insensitive power amplifier power detector may include a voltage sampling circuit in electrical communication with a collector of a power amplifier and configured to sample a first voltage from the power amplifier. The load-insensitive power amplifier power detector may include a current sampling circuit in electrical communication with the collector of the power amplifier and configured to sample an output current from the power amplifier. Further, the load-insensitive power amplifier power detector may include a current-to-voltage converter connected between the voltage sampling circuit and an output of the load-insensitive power amplifier power detector. The current-to-voltage converter may be configured to convert the output current to obtain a second voltage. Moreover, a combination of the first voltage and the second voltage may form a detector voltage corresponding to an incident power of the power amplifier.
SEMICONDUCTOR DEVICE AND POWER AMPLIFIER CIRCUIT
A semiconductor device includes a semiconductor substrate and first and second bipolar transistors. The semiconductor substrate includes first and second main surfaces opposing each other. The first bipolar transistor is formed on the first main surface of the semiconductor substrate and includes a first emitter layer. The second bipolar transistor is formed on the first main surface of the semiconductor substrate and includes a second emitter layer and a resistor layer. The resistor layer is stacked on the second emitter layer in a direction normal to the first main surface.