A half-power buffer amplifier includes an amplification unit including first and second nodes, the amplification unit configured to differentially amplify a differential input signal and to output a differentially amplified output signal, a first output unit including a first buffer unit between a first power source having a first voltage and a second power source having a second voltage, a second buffer unit between the first and second power sources, and a first switch unit between the first and second buffer units, and a second output unit including a third buffer unit between the second power source and a third power source having a third voltage, a fourth buffer unit between the second and third power sources, and a second switch unit between the third and fourth buffer units. Each of the first to third buffer units receives the differentially amplified output signal. The first switch unit is turned on or off based on or in response to a pre-driving control signal.

A half-power buffer amplifier is disclosed. The amplifier includes an amplification unit configured to differentially amplify differential input signals, the amplification unit including nodes configured to output differentially amplified first to fourth output signals, a first output buffer unit including first and second transistors, and an output node to which the first and second transistors are connected, a second output buffer unit including third and fourth transistors, wherein the third and fourth transistors are connected to the output node, a first control switch between the first output node and the second transistor and controlled by a polarity control signal, and a second control switch between the second output node and the third transistor and controlled by a complement of the polarity control signal.

Disclosed is an amplifier capable of minimizing shortcircuit current of an output stage of a buffer upon transition of an output voltage while having a high slew rate without increasing power consumption. The amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, and a short-circuit current minimization circuit. Alternatively, the amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, a short-circuit current minimization circuit, and a slew rate improvement circuit.

An operational amplifier circuit includes an operational amplifier and a control circuit. The operational amplifier includes a first input terminal, a second input terminal, and an output terminal connected with the second input terminal. The operational amplifier amplifies a signal provided through the first input terminal, and outputs the amplified signal through the output terminal. The control circuit generates switching signals. In response to the switching signals, the operational amplifier resets the output terminal to a preset voltage, charges the reset output terminal, and compares a voltage of the output terminal charged with a reference voltage provided through the first input terminal to output a comparison voltage.

A buffer amplifier circuit includes a buffer amplifier including a first differential amplifier having a first active load and a second differential amplifier having a second active load and a feedback circuit configured to feed an output signal of an output terminal of the buffer amplifier back to one of the first and second active loads using differential switch signals and an input signal of the buffer amplifier to enhance a slew rate of the output signal.

An amplifier includes a differential input stage, a hysteresis stage, coupled to the differential input stage, a cascode stage coupled to the hysteresis stage, a feedback stage coupled to an output of the cascode stage and configured to provide a feedback signal to the hysteresis stage, and an output stage coupled to the output of the cascode stage. The output stage includes a hysteresis inverter coupled between the output of the cascode stage and the amplifier output.

An amplifier includes a differential input stage, a hysteresis stage, coupled to the differential input stage, a cascode stage coupled to the hysteresis stage, a feedback stage coupled to an output of the cascode stage and configured to provide a feedback signal to the hysteresis stage, and an output stage coupled to the output of the cascode stage. The output stage includes a hysteresis inverter coupled between the output of the cascode stage and the amplifier output.

An operational amplifier circuit is provided. The operational amplifier circuit includes a differential input stage circuit and a loading stage circuit. The differential input stage circuit includes an input circuit, a voltage maintaining circuit, and a current source. The input circuit includes a first input transistor and a second input transistor, for receiving a first and a second input signals, respectively. The voltage maintaining circuit includes a first branch circuit and a second branch circuit. The first branch circuit is coupled to the first input transistor for receiving the first input signal, and the second branch circuit is coupled to the second input transistor for receiving the second input signal. The current source is coupled to the first input transistor and the second input transistor. The loading stage circuit is coupled to the voltage maintaining circuit.

A buffer amplifier configured to perform voltage switching (DC bias voltage switching). The buffer amplifier includes first and second amplification blocks corresponding to first and second channels, respectively, first and second output buffer units controlled by output levels of the first and second amplification blocks, and a switch unit configured to connect or disconnect the first or second amplification block to or from the first or second output buffer unit. The switch unit includes a first switch unit configured to connect or disconnect one of the first and second amplification blocks to or from the first output buffer unit based on or in response to a control signal and a second switch unit configured to connect or disconnect another one of the first and second amplification blocks to or from the second output buffer unit based on or in response to the control signal.

An apparatus to prevent supply-to-ground current in a comparator is disclosed. The apparatus includes circuitry to determine if first and second output nodes of the comparator have respectively reached first and second logic levels, and circuitry responsive to a determination that the voltage at the first and second output nodes of the comparator has reached the first and second logic levels, to generate a signal. In addition, the apparatus includes circuitry to supply the signal to a transistor, the signal to turn off the transistor and prevent the flow of supply-to-ground current through the comparator.