A signal processing circuit amplifies a signal of a magnetic sensor that changes according to the magnitude of a magnetic force. The signal of the magnetic sensor is a pair of signals inverted from each other with respect to a reference voltage. The signal processing circuit includes: a high-pass filter that performs a high-pass filtering process on the complementary signals from the magnetic sensor; a differential amplifier that receives the complementary signals having been subjected to the high-pass filtering process by the high-pass filter as a differential input signal and amplifies the differential input signal at a predetermined amplification factor based on the reference voltage; and a comparator that outputs a binary signal indicating a comparison result between an output signal of the differential amplifier and the reference voltage.

Disclosed herein is a circuit including a differential amplifier having a pair of input transistors coupled in a differential arrangement between adjustable current sources and receiving input differential signals from a pair of input voltage regulators. The adjustable current sources are configured to source more current to the pair of input transistors than current that is sunk from the pair of input transistors. A first amplifier has inputs coupled to receive differential output voltages from the differential amplifier. A second amplifier has inputs coupled to receive amplified differential output voltages from the first amplifier. A low pass filter has inputs coupled to receive further amplified differential output voltages from the second amplifier and produce final differential output voltages.

In accordance with aspects of the present invention, embodiments of a photodiode circuit. A photodiode circuit according to some embodiments includes a transimpedance amplifier; a resistor coupled across the transimpedance amplifier; and an amplifier stage coupled to receive an output from the transimpedance amplifier, wherein the photodiode circuit provides dynamic range across a current range of the photodiode circuit. In some embodiments, the transimpedance amplifier includes a receive signal strength indicator that provides a DC current signal to a tail of a first amplifier stage, the tail providing a current that is adaptively related to the DC current. In some embodiments, the resistor is a shielded resistor. In some embodiments, the adaptive current sink includes a plurality of switchable parallel current sinks.

The present application discloses an amplifier circuit, a chip and an electronic device, which generates a positive output signal and a negative output signal according to a positive input signal and a negative input signal, wherein the positive input signal and the negative input signal have a corresponding input differential-mode voltage and input common-mode voltage, and the positive output signal and the negative output signal have a corresponding output differential-mode voltage and output common-mode voltage, and the amplifier circuit includes: an amplifying unit, configured to receive the positive input signal and the negative input signal and generate the positive output signal and the negative output signal; and an attenuation unit, including: a positive common-mode capacitor and a negative common-mode capacitor, configured to attenuate the input common-mode voltage below a first specific frequency.

A limiting amplifier circuitry according to the disclosure includes: a first differential amplifier circuitry capable of adjusting, as voltage offset, a difference between direct-current voltage components of first differential signals input thereto, the first differential amplifier circuitry amplifying the first differential signals and outputting the amplified first differential signals as second differential signals; a second differential amplifier circuitry that amplifies the second differential signals with an amplification factor depending on a difference between direct-current voltage components of the second differential signals; a signal detecting circuitry that detects an amplitude of the second differential signals, determines whether or not the amplitude is larger than a threshold, and outputs a determination result; and an offset control circuitry that controls the voltage offset by using the determination result.

In optical receivers, cancelling the DC component of the incoming current is a key to increasing the receiver's effectiveness, and therefore increase the channel capacity. Ideally, the receiver includes a DC cancellation circuit for removing the DC component; however, in differential receivers an offset may be created between the output voltage components caused by the various amplifiers. Accordingly, an offset cancellation circuit is required to determine the offset and to modify the DC cancellation circuit accordingly.

A voltage regulator with a load line circuit is disclosed. The load line circuit is configured to receive a sensed voltage corresponding to an output current of the voltage regulator. The load line circuit is further configured to generate a complex (e.g., nonlinear) load line voltage that is combined with the output voltage of the voltage regulator and compared with a set voltage of the voltage regulator to produce an error signal. The error signal is used as feedback for the voltage regulator so that the output voltage of the voltage regulator can droop by a particular amount corresponding to a particular output current of the voltage regulator. The disclosed analog approach requires neither clock signals nor digital circuitry and utilizes a parallel topology that allows the disclosed approach to be fast and energy efficient.

Within a modulator driver, different blocks are employed, e.g. a buffer, one or more variable gain amplifiers (VGA), and a final driver stage. Each of these blocks has an optimum bias point for best performance; however, interconnecting the blocks requires sharing the DC bias points in their interface, which does not necessarily match the optimum performance bias point of each block. Accordingly, a first offset feedback loop extending from reference points after a selected one of the blocks to an input of one of the blocks. The first offset feedback loop includes current sources capable of delivering a variable current to the input of the selected block in order to compensate any offset in an amplified differential input electrical signal measured at the reference points. A first bias feedback loop is also provided, including a current sinker for subtracting excess current introduced in the first offset compensation feedback loop.

An amplifier device includes an amplifier circuitry, a controller circuitry, and an offset cancellation circuitry. The amplifier circuitry is configured to amplify a first input signal and a second input signal, in order to generate a first output signal and a second output signal. The controller circuitry is configured to generate a first control signal and a second control signal according to the first output signal and the second output signal. The offset cancellation circuitry is configured to provide a negative capacitor to the amplifier circuitry, and to adjust at least one current flowing through a circuit, which provides the negative capacitor, of the offset cancellation circuitry according to the first control signal and the second control signal, in order to cancel an offset of the amplifier circuitry.

A voltage regulator with a load line circuit is disclosed. The load line circuit is configured to receive a sensed voltage corresponding to an output current of the voltage regulator. The load line circuit is further configured to generate a complex (e.g., nonlinear) load line voltage that is combined with the output voltage of the voltage regulator and compared with a set voltage of the voltage regulator to produce an error signal. The error signal is used as feedback for the voltage regulator so that the output voltage of the voltage regulator can droop by a particular amount corresponding to a particular output current of the voltage regulator. The disclosed analog approach requires neither clock signals nor digital circuitry and utilizes a parallel topology that allows the disclosed approach to be fast and energy efficient.