A sequential circuit includes a first gate circuit, a second gate circuit and an output circuit. The first circuit generates a first signal based on an input signal, an input clock signal and a second signal. The second circuit generates an internal clock signal by performing a NOR operation on the first signal and an inversion clock signal which is inverted from the input clock signal, and generates the second signal based on the internal clock signal and the input signal. The output circuit generates an output signal based on the second signal. Operation speed of the sequential circuit and the integrated circuit including the same may be increased by increasing the negative setup time reflecting a transition of the input signal after a transition of the input clock signal, through mutual controls between the first circuit and the second circuit.

A circuit and an array circuit for implementing a shift operation are provided. The circuit for implementing a shift operation includes a resistive random-access memory and four switches. The circuit has a simple structure and can improve computational efficiency.

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first stage that receives an enable signal and an input clock signal and provides a first intermediate signal based on the enable signal and the input clock signal. The integrated circuit may include a second stage that receives the first intermediate signal and the input clock signal and provides a second intermediate signal based on a ternary logic response to the first intermediate signal and the input clock signal. The integrated circuit may include a third stage that receives the second intermediate signal and the input clock signal and provides an output clock signal based on the second intermediate signal and the input clock signal.

A flip-flop element is configured to include FinFET technology transistors with a mix of threshold voltage levels. The data input path includes FinFET transistors configured with high voltage thresholds (HVT). The clock input path includes transistors configured with standard voltage thresholds (SVT). By including FinFET transistors with SVT thresholds in the clock signal path, the Miller capacitance of the clock signal path is reduced relative to HVT FinFET transistors, leading to lower rise time and correspondingly lower hold time. By including HVT threshold devices in the data input path, the flip-flop element attains high speed and low power operation. By including SVT threshold devices in the clock signal path, the flip-flop element achieves faster switching times in the clock signal path.

Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.

A register and an analog-digital converter capable of detecting signal distortion in high-radiation environments are provided. The register includes: a signal input terminal receiving a digital signal; and a digital single event transient (DSET) detection unit detecting whether information of the digital signal input through the signal input terminal is distorted, wherein the DSET detection unit includes a first output terminal through which a first detection signal is output, the first detection signal being used to determine whether at least one of rising edge timing information and falling edge timing information of the digital signal is distorted.

There is disclosed herein multiplexer circuitry. In particular, there is disclosed a latch circuit for use as a multiplexer to multiplex information carried by respective pairs of input information signals onto an output information signal, each pair of input information signals comprising a first input information signal and a second input information signal, and each pair of input information signals carrying information values based on signal values of those input information signals and interleaved with information values carried by the other pair or pairs of input information signals.

Aspects of the disclosure provide a circuit having a pulse latch circuit and an enable circuit. The latch circuit is configured to receive a first signal at an input lead and drive the first signal to an output lead in response to an enable signal. The enable circuit is configured to be active to generate the enable signal to enable the latch circuit to receive the first signal when the first signal is different from a second signal on the output lead and is configured to default the enable signal to suppress the first signal so as not to be received at the latch circuit when the first signal is the same as the second signal.

Disclosed are a latch circuit receiving a negative output of a next stage latch circuit as a feedback input, a double data rate (DDR) ring counter based on the latch circuit to perform DDR counting of pulse periods and reduce the number of toggles, a hybrid counting device counting lower-bit portion by using the latch-based DDR ring counter and upper-bit portion by using a binary counter, and an analog-to-digital converting device and a CMOS image sensor employing the hybrid counting device. A double data rate ring counter may include a plurality of latches coupled in a ring type. The plurality of latches may include positive-edge-triggered latches and negative-edge-triggered latches arranged alternately. A current stage latch receives an output of a previous latch stage to shift to a next latch stage according to a counter clock, receives an output of the next latch stage to check a data shift to the next latch stage, and falls to a low level if the data shift is checked.

A flip-flop includes a first set of transistors of a first type being located in a first row and a second set of transistors of a second type being located in a second row. The second type being different from the first type. The first and second set of transistors include a first master latch circuit and a second master latch circuit. The first and second master latch circuit are separated from each other in the first direction by a first distance. A first output signal of the first and second master latch circuit is a first input signal of the first master latch circuit and the second master latch circuit. A second output signal of the first and second master latch circuit is a second input signal of the first and second master latch circuit.