A circuit, method, and system are disclosed for sampling a signal. The system includes a sampler circuit configured to sample input signals when a clock signal is at a first voltage level to produce sampled signals, a detection circuit that is coupled to the sampler circuit, and a feedback circuit that receives an output signal and generates the clock signal. The detection circuit pre-charges the sampled signals when the clock signal is at a second voltage level and, using threshold adjusted inverters, detects voltage levels of each sampled signal to produce detected voltage levels, where a threshold voltage of the threshold adjusted inverters is entirely outside of a transition voltage range of the sampler circuit. In response to one of the detected voltage levels transitioning from the second level to the first level, the detection circuit transitions the output signal from the first voltage level to the second voltage level.

A circuit, method, and system are disclosed for sampling a signal. The system includes a sampler circuit configured to sample input signals when a clock signal is at a first voltage level to produce sampled signals, a detection circuit that is coupled to the sampler circuit, and a feedback circuit that receives an output signal and generates the clock signal. The detection circuit pre-charges the sampled signals when the clock signal is at a second voltage level and, using threshold adjusted inverters, detects voltage levels of each sampled signal to produce detected voltage levels, where a threshold voltage of the threshold adjusted inverters is entirely outside of a transition voltage range of the sampler circuit. In response to one of the detected voltage levels transitioning from the second level to the first level, the detection circuit transitions the output signal from the first voltage level to the second voltage level.

A circuit, method, and system are disclosed for sampling a signal. The system includes a sampler circuit configured to sample input signals when a clock signal is at a first level to produce sampled signals, a detection circuit that is coupled to the sampler circuit, and a feedback circuit that receives an output signal and generates the clock signal. The detection circuit pre-charges the sampled signals when the clock signal is at a second level and, using threshold adjusted inverters, detects voltage levels of each sampled signal to produce detected voltage level signals, where a threshold voltage of the threshold adjusted inverters is entirely outside of a transition voltage range of the sampler circuit. In response to one of the detected voltage level signals transitioning from the second level to the first level, the detection circuit transitions the output signal from the first level to the second level.

Techniques are disclosed relating to level-shifting circuitry and time borrowing across voltage domains. In disclosed embodiments, an apparatus includes pulse circuitry, latch circuitry, pull circuitry, and feedback circuitry. The pulse circuitry is configured to generate a pulse signal in response to an active clock edge. The latch circuitry is configured to store a value of an input signal, where the input signal has a first voltage level. The pull circuitry is configured to drive, during the pulse signal, an output of the latch circuitry to match a logical value of the input signal at a second, different voltage level. This may allow the input signal to change during the pulse, enabling time borrowing. The feedback circuitry is configured to maintain the output of the latch circuitry at the second voltage level after the pulse signal.

Provided are semiconductor circuits. A semiconductor circuit includes: a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.

A level shifter is configured to receive an input signal in a first voltage domain and output an output signal in a second voltage domain. An input terminal is configured to receive an input signal in a first voltage domain. A first sensing circuit is configured to shift the input signal from the first voltage domain to the second voltage domain, and a second sensing circuit is configured to shift the input signal from the first voltage domain to the second voltage domain. An enable circuit is configured to equalize a voltage level of first and second output signals at respective first and second output terminals in response to an enable signal. The first and second sensing circuits are configured output complementary output signals in the second voltage domain at the first and second output terminals in response to the enable signal and the input signal.

In one form, a power supply monitor including a current controlled oscillator circuit, a time-to-digital converter, and an output divider. The current controlled oscillator circuit has an input for receiving a power supply voltage to be measured, and an output for providing a frequency signal having a frequency linearly proportional to the power supply voltage. The time-to-digital converter has an input coupled to the output of the current controlled oscillator circuit, and an output for providing a count signal representative of a number of cycles of a reference clock signal per cycle of the frequency signal. The output divider has an input coupled to the output of the time-to-digital converter, and an output for providing a divided count signal representative of a value of the power supply voltage, and provides the divided count signal by dividing a fixed number by the count signal.

The present technology may include a first detection unit configured to generate an output signal by detecting a level of an input terminal in response to a transition of a control clock signal during a normal read operation, and a second detection unit configured to generate the output signal by detecting the level of the input terminal regardless of the transition of the control clock signal during a state information read operation.

A comparator is described. The comparator may be used in several applications, including in digital-to-analog converters (ADC). The comparator may comprise a high-speed amplifier, a low-noise amplifier, a controller and a bi-stable circuit. The high-speed amplifier may be activated during a first period, for example when the comparator tends to exhibit a slow response. During this period, the comparator may sacrifice the noise performance. The low-noise amplifier may be activated during a second period, for example when the difference between the signals appearing as inputs to the comparator is small. The low-noise amplifier may have a gain that is large enough to limit decision errors. The bi-stable circuit, which may be implemented using a latch, may be configured to output a signal equal to one of the supply voltages, in response to receiving the input signal from one of the stages.

A level shifter comprises a first control switch (207) for connecting an output terminal to a first supply voltage (VDDH) to set an output signal to be high, and a second control switch (208) for connecting the output terminal to a signal ground (GND) to set the output signal to be low. The level shifter comprises a pre-charging switch (210) for connecting the output terminal to the first supply voltage, and an input gate circuit (211) for controlling an ability of an input signal to control the second control switch. The level shifter comprises a keeper circuit (212) for controlling the first control switch based on the output signal. The first control switch is controlled with the first supply voltage when the output signal is low, and with a second supply voltage that is between the first supply voltage and the signal ground when the output signal is high.