A digital-to-analog converter (DAC) includes a current array having a plurality of unit cells in a plurality of rows and a plurality of columns, an arbitrary switch box and processing circuitry configured to randomly select a subset of rows among the plurality of rows based on a plurality of first row selection signals, the subset of rows including first unit cells among the plurality of unit cells, randomly select one row among the plurality of rows based on a plurality of second row selection signals, select a subset of columns among the plurality of columns based on column selection signals, second unit cells among the plurality of unit cells being included in both the one row and the subset of columns, and generate an analog output signal corresponding to a digital input signal based on the first unit cells and the second unit cells.

A successive approximation register analog-to-digital converter (SAR ADC) circuit comprises N weighted bit capacitors, wherein N is a positive integer greater than one; a sampling circuit configured to sample an input voltage onto the N weighted bit capacitors; and logic circuitry. The logic circuitry is configured to enable sampling of the input voltage onto the N weighted bit capacitors in a high-resolution mode; enable sampling of the input voltage onto NM of the weighted bit capacitors in a low-resolution mode and sampling a common mode voltage onto the most significant M weighted bit capacitors, wherein M is a positive integer greater than zero and less than N; and initiate successive bit trials using the weighted bit capacitors to convert the sampled input voltage to a digital value.

A multi-step analog-to-digital converter (ADC). The ADC includes a sampling circuitry, a comparator, a trimming circuitry, and a DC offset actuator. The sampling circuitry is configured to sample an input analog signal. The comparator is for comparing the input analog signal sample or a residual component of the input analog signal sample to a reference value in each step. The trimming circuitry is configured to receive at least one low-order bit (e.g., a least significant bit and/or a second-least significant bit) of digital binary bits of each input analog signal sample and average the low order bit over a plurality of input analog signal samples and generate a control signal for correcting an input DC offset of the comparator based on an average value of the low-order bits. The DC offset actuator is configured to correct the input DC offset of the comparator based on the control signal.

A pixel circuit and method for operating the same is disclosed. The circuit includes a first driver circuit coupled to receive an analog pixel data, transfer signal and reset signal. The circuit further includes a source follower transistor having a source terminal coupled to a column node, and a gate terminal coupled to the first driver circuit. The circuit further includes a second driver circuit coupled to receive the transfer signal and the reset signal. The second driver circuit is capacitively coupled to the column node through a first capacitor.

The present invention provides a time-interleaved analog-to-digital converter device, wherein the time-interleaved analog-to-digital converter device includes a random number generator, a plurality of ADCs and an output circuit. The random number generator is configured to generate a random number sequence. The plurality of ADCs are configured to receive an analog input signal to generate a plurality of digital signals, respectively, and each ADC is further configured to generate a selection signal according to the random number sequence. The output circuit is configured to select one of the digital signals according to the selection signals generated by the ADCs, to generate a digital output signal.

A system includes an input shuffling circuit and digital-to-analog conversion circuitry. The input shuffling circuit includes a data input, a data output, and a control input. The input shuffling circuit is operable to receive, via the data input, an N-bit binary value, where N is an integer. The input shuffling circuit is operable to route each of the N bits of the N-bit binary word to one or more of M bits of the data output to generate an M-bit value, where M=2N, and the routing is based on a control value applied to the control input. The input shuffling circuit can be configured either in a dynamic element matching (DEM) mode or a regular binary to thermometer mode. The digital-to-analog conversion circuitry is operable to convert the M-bit value to a corresponding analog voltage and/or current. M different values of the control value may result in M different routings of the N bits of the binary word.

A frequency digital-to-analog converter (FDAC) for generating an analog frequency modulating signal from a digital frequency modulating signal includes a Least Significant Bit (LSB) DAC section and a Most Significant Bit (MSB) DAC section. The LSB DAC section comprises a plurality of LSB DACs and is configured to switch between the LSB DACs for mitigating mismatch. The MSB DAC section comprises a plurality of MSB DAC cells and is configured to switch the MSB DAC cells according to a predefined sequence during a period of the digital frequency modulating signal.

A TI ADC circuit (30) comprises a plurality of L analog inputs (32-1, 32-2, 32-3) and a plurality of L digital outputs (34-1, 34-2, 34-3). The i:th analog input (32-i) is for receiving an i:th analog input signal. The i:th digital output (34-i) is for outputting an i:th digital output signal, which is a digital representation of the i:th analog input signal. TI ADC circuit (30) comprises a set (90) of sub ADCs (100-1100-K). The TI ADC circuit (30) is configured to generate one sample of each of the L digital output signals per conversion cycle. Each sub ADC (100-1100-K) is configured to generate a digital output sample in M conversion cycles, wherein M is an integer >1. The number K of sub ADCs in the set (90) of sub ADCs (100-1100-K) exceeds L.Math.M. TI ADC circuit (30) comprises a control circuit (120) configured to select, for each input sample of each of the L analog input signals, which available sub ADC (100-1100-K) in the set (90) of sub ADCs that should operate on that input sample, such that at least some of the sub ADCs (100-1100-K), over time, operate on input samples of each of the L analog input signals.

An analog-to-digital converter (ADC) and a method are disclosed. The ADC has a quantizer. The quantizer comprises a linear-feedback shift register (LFSR), a decoder configured to provide a plurality of switch control signals at a plurality of decoder outputs, respectively, the plurality of switch control signals responsive to a LFSR value of the LFSR output; an electrical reference, the electrical reference having a plurality of reference outputs, the electrical reference configured to provide a plurality of reference levels at the plurality of reference outputs, respectively; a first switch providing a first switch output and a second switch output; and a comparator, the comparator having a signal input, a first reference input, and a second reference input, the first reference input connected to the first switch output, and the second reference input connected to the second switch output.

An apparatus comprising M time-interleaved analog to digital converters (ADC) that sample an input signal at M sampling phases, wherein M is equal to or greater than 4. A phase control circuit adjusts at least M1 sampling phases of the M sampling phases. The phase control circuit comprises M1 phase error detector circuits. Each phase error detector circuit detects a corresponding phase error for a corresponding sampling phase of the M1 sampling phases based on a sample captured at a sampling phase of the M sampling phases immediately preceding the corresponding sampling phase and a sample captured at a sampling phase of the M sampling phases immediately subsequent to the corresponding sampling phase.