The present invention provides a fractional-N frequency synthesizer comprising a divider controller comprising a multistage noise Shaping (MASH) digital delta-sigma modulator comprising L stages, wherein the Lth stage is configured to receive as an input a high amplitude dither signal.

An analog-to-digital convertor circuit converts the output of a loop filter circuit to a digital signal. A random sequence generation circuit generates a random sequence. Adder circuitry adds the random sequence to the digital signal to generate a randomized digital signal. Noise transfer function impulse response detection circuitry processes the randomized digital signal and the random sequence to determine a noise transfer function impulse response. Loop filter configuration circuitry configures the loop filter circuit based on the noise transfer function impulse response. The random sequence generation circuit may comprises a high-pass sigma delta modulator. The noise transfer function impulse response detection circuitry may determine the noise transfer function impulse response, and the loop filter configuration circuitry may configure the loop filter based on the noise transfer function impulse response. The loop filter configuration circuitry may generate loop filter coefficients based on the noise transfer function impulse response.

An audio activity detector device is disclosed. The audio activity detector device comprises a closed loop feedback regulating circuit that supplies an input signal representative of a time-varying voltage signal to a quantizer circuit, wherein the quantizer circuit, as a function of the input signal, converts the input signal to a quantizer discrete-time signal; a first circuit that, as a function of the discrete-time signal, determines a key quantizer statistic value for the quantizer discrete-time signal; and a second circuit that, as a function of the key quantizer statistic value, determines a signal statistic value for the input signal and a gain control value.

In accordance with an embodiment, a method includes adding a dither signal to a first signal to generate a second signal, subtracting the dither signal from the first signal or subtracting the first signal from the dither signal to generate a third signal, performing a first sigma delta conversion of the second signal to a digital fourth signal, performing a second signal delta conversion of the third signal to a digital fifth signal, combining the digital fourth signal and the digital fifth signal to form a digital sixth signal.

In accordance with an embodiment, a method includes adding a dither signal to a first signal to generate a second signal, subtracting the dither signal from the first signal or subtracting the first signal from the dither signal to generate a third signal, performing a first sigma delta conversion of the second signal to a digital fourth signal, performing a second signal delta conversion of the third signal to a digital fifth signal, combining the digital fourth signal and the digital fifth signal to form a digital sixth signal.

The present invention provides a fractional-N frequency synthesizer comprising a divider controller comprising a multistage noise Shaping (MASH) digital delta-sigma modulator comprising L stages, wherein the Lth stage is configured to receive as an input a high amplitude dither signal.

The disclosed invention is a sigma-delta modulator based ADC and a dithering method thereof. An analog dither circuit of an input stage in a quantizer, which is configured to perform dithering, receives an integrator output signal from an output of an integrator and a plurality of digital dither signals from digital dither generator, and employs these signals to produce multi-level analog dither signals via the operation of a plurality of transistors as switches coupled with a plurality of resistors coupled in series. The multi-level analog dither signals can prevent, reduce, or eliminate limit cycle in the sigma-delta modulator based ADC. Furthermore, disclosed invention does not require fixed load capacitance, resulting in no extra power consumption and solve the problem as the kickback noise variation.

Techniques for generating signals with arbitrary noise shaping are discussed. One example apparatus configured to be employed within a transmitter can comprise a noise shaper configured to: receive an input signal x.sub.q; and apply noise shaping to the input signal x.sub.q to generate a noise shaped output signal y.sub.q, wherein an in-band noise of the noise shaped output signal y.sub.q is below an in-band noise threshold of a spectral mask associated with the noise shaper, wherein an out-of-band noise of the noise shaped output signal y.sub.q is below an out-of-band noise threshold of the spectral mask, and wherein a noise of the output signal y.sub.q in each of a plurality of bandpass regions is below an associated noise threshold for that bandpass region of the spectral mask.

A higher accuracy ADC circuit (e.g., in which the number of bits of the ADC circuit is twelve or greater) may need calibration multiple times during its working life to avoid bit weight errors. Described are techniques to address DAC element ratio errors between DAC element clusters in a DAC circuit in order to maintain the linear performance of analog-to-digital converter (ADC) circuits and digital-to-analog converter (DAC) circuits.

An apparatus (100) comprises a signal generator (101) that is set up to produce a digital random signal (191). The apparatus (100) also comprises at least one filter element (102, 121, 122) that is set up to apply a high pass filter and a low pass filter to the digital random signal (191) in order to produce a spectrally shaped random signal (112). The apparatus (100) also comprises a modulator (103) that is set up to apply the spectrally shaped random signal (192) as dither.