A method includes receiving samples of digital to analog converter (DAC), partitioning the samples to unit-DACs based upon previous partitions of inputs to the unit-DACs to cancel out integrated non-linearities of outputs of the DAC caused by the gain mismatches of the unit-DACs, including partitioning samples of DAC input to the unit-DACs through a recursive nth order partitioning algorithm. The algorithm includes, for each DAC input, determining a first partition of the DAC input that would cancel an (n1)th order previously integrated non-linearity, adding an equivalent DAC input of the first partition to the DAC input to obtain a total DAC input, using a first order application of the total DAC input to the inputs of the unit-DACs to yield a second partition of DAC input, summing the first and second partitions generate a final partition, and, based on the final partition, computing non-linearity remainders at each order of integration.

A variable feedback gain delta modulator includes group of capacitors commonly connected to a first terminal and are respectively classified into a first capacitor group and a second capacitor group; a comparator for sequentially generating n-bit digital output signals based on a voltage of the first terminal; and a switch group including switches respectively connected to the capacitors, wherein the switches are respectively classified into a first switch group and a second switch group respectively connected to the first capacitor group and the second capacitor group, and the first switch group and the second switch group respectively operate according to a first control signal and a second control signal that are determined based on the n-bit digital output signals and the variable feedback gain.

Embodiments of an apparatus for direct coupling of a capacitive sensor to a delta-sigma converter are described. One apparatus includes a sensor, a charge coupling circuit configured to transfer at least a portion of charge generated by the sensor to an integrating circuit, a first charge feedback circuit configured to feed back charge to the sensor, a second charge feedback circuit configured to feed back charge to the integrating circuit, a comparing circuit configured to detect accumulated charge at the integrating circuit for a current cycle to determine a polarity of charge feedback for a subsequent cycle, and a logic circuit configured to provide a digital output corresponding to the sensed quantity and also configured to provide the polarity of charge feedback determined by the comparing circuit to the first charge feedback circuit and also to the second charge feedback circuit.

A delta-sigma modulator including force circuitry that receives an output digital signal and provides a forced digital signal with a predetermined force state based on a force control signal, a combiner that subtracts the forced digital signal from the output digital signal for providing a digital error signal, and force correction circuitry that converts the digital error signal into one or more analog error correction signals applied to corresponding inputs of loop filter circuitry. The digital error signal and the force control signal may each be used to develop corresponding analog feedback signals used to adjust an analog input signal. The digital error signal may also be converted to one or more correction signals applied to corresponding inputs of the loop filter circuitry to correct the output digital signal. The digital error signal may also be used by a digital noise cancellation filter to further correct the output digital signal.

A self-reset ADC may take a set of temporally equidistant, modulo samples of a bandlimited, analog signal, at a sampling rate that is greater than e samples per second, where is Archimedes' constant and is Euler's number. The bandlimited signal may have a bandwidth of 1 Hertz and a maximum frequency of 0.5 Hertz. These conditions of sampling rate, bandwidth and maximum frequency may ensure that an estimated signal may be recovered from the set of modulo samples. This estimated signal may be equal to the bandlimited signal plus a constant. The constant may be equal to an integer multiple of the modulus of the centered modulo operation employed to take the modulo samples.

The present invention provides a fractional-N frequency synthesizer comprising a divider controller comprising a multistage noise Shaping (MASH) digital delta-sigma modulator comprising L stages, wherein the Lth stage is configured to receive as an input a high amplitude dither signal.

A variable feedback gain delta modulator includes group of capacitors commonly connected to a first terminal and are respectively classified into a first capacitor group and a second capacitor group; a comparator for sequentially generating n-bit digital output signals based on a voltage of the first terminal; and a switch group including switches respectively connected to the capacitors, wherein the switches are respectively classified into a first switch group and a second switch group respectively connected to the first capacitor group and the second capacitor group, and the first switch group and the second switch group respectively operate according to a first control signal and a second control signal that are determined based on the n-bit digital output signals and the variable feedback gain.

A variable feedback gain delta modulator includes group of capacitors commonly connected to a first terminal and are respectively classified into a first capacitor group and a second capacitor group; a comparator for sequentially generating n-bit digital output signals based on a voltage of the first terminal; and a switch group including switches respectively connected to the capacitors, wherein the switches are respectively classified into a first switch group and a second switch group respectively connected to the first capacitor group and the second capacitor group, and the first switch group and the second switch group respectively operate according to a first control signal and a second control signal that are determined based on the n-bit digital output signals and the variable feedback gain.

A variable feedback gain delta modulator includes group of capacitors commonly connected to a first terminal and are respectively classified into a first capacitor group and a second capacitor group; a comparator for sequentially generating n-bit digital output signals based on a voltage of the first terminal; and a switch group including switches respectively connected to the capacitors, wherein the switches are respectively classified into a first switch group and a second switch group respectively connected to the first capacitor group and the second capacitor group, and the first switch group and the second switch group respectively operate according to a first control signal and a second control signal that are determined based on the n-bit digital output signals and the variable feedback gain.

An error feedback system for a delta sigma modulator is disclosed. The error feedback system has an error transfer function where at least k1 coefficients are set to zero. This allows the error feedback system to be divided into k feedback paths that are performed in parallel at a clock speed that is 1/k of the system clock of the delta sigma modulator (i.e. the rate at which the output of the delta sigma modulator changes).