Methods and systems for decoding raw data may include determining a sequence of a plurality of read-level voltages based on previous decoding data and executing a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read-level voltages. Decoded data is returned from the multi-stage decoding operation upon completion of the multi-stage decoding operation and the previous decoding data is updated based on results of the multi-stage decoding operation.

According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.

According to one embodiment, a decoding device comprises a converter configured to convert read data to first likelihood information by using a first conversion table, a decoder which decodes the first likelihood information, a controller which outputs a decoding result of the decoder when the decoder succeeds decoding, and a creator module which creates a second conversion table based on the decoding result when the decoder fails decoding. When the second conversion table is created, at least a part of the decoding result is converted to second likelihood information by using the second conversion table the second likelihood information is decoded.

Examples relate to a Low-Density Parity-Check Code (LDPC) decoder apparatus or device, to an LDPC decoder system and to corresponding methods and computer programs. The LDPC decoder apparatus comprises input circuitry and processing circuitry. The processing circuitry is configured to obtain a syndrome of a codeword via the input circuitry. The processing circuitry is configured to perform LDPC iterative decoding using the obtained syndrome, wherein the changes to be applied to the codeword due to the LDPC iterative decoding are recorded by applying the changes to a surrogate codeword. The processing circuitry is configured to record changes to be applied to the codeword due to the LDPC iterative decoding by storing the surrogate codeword in a memory structure.

An operating method of a memory controller is provided. The operating method includes receiving a first read data and a second conversion information, the second conversion information including data obtained by converting a second read data based on a linear operation, and the first read data and the second read data including data read from same memory cells; converting the first read data based on the linear operation to generate a first conversion information; performing a logical operation on the first conversion information and the second conversion information to generate an operation information; performing an inverse operation of the linear operation on the operation information to generate a reliability information; and correcting an error of the first read data based on the first read data and the reliability information.

Devices, systems and methods for reducing complexity of a bit-flipping decoder for quasi-cyclic (QC) low-density parity-check (LDPC) codes are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from an irregular QC-LDPC code, the irregular QC-LDPC code having an associated parity matrix, storing, based on a weight of a plurality of columns of the parity matrix of the irregular QC-LDPC code, a portion of the noisy codeword corresponding to the plurality of columns in a first buffer of a plurality of buffers, and accessing and processing the portion of the noisy codeword that includes applying a vertically shuffled scheduling (VSS) scheme that uses a plurality of processing units to determine a candidate version of a portion of the transmitted codeword that corresponds to the portion of the noisy codeword.

This invention presents a method and the corresponding hardware apparatus for decoding LDPC codes using a vertical layered (VL) iterative message passing algorithm. The invention operates on quasi-cyclic LDPC (QC-LDPC) codes, for which the non-zero circulant permutation matrices (CPMs) are placed at specific locations in the parity-check matrix of the codes, forming concentrated clusters of CPMs. The purpose of the invention is to take advantage of the organization of CPMs in clusters in order to derive a specific hardware architecture, consuming less power than the classical VL decoders. This is achieved by minimizing the number of read and write accesses to the main memories of the design.

Embodiments of the present disclosure relate to a method and apparatus for data processing in a communication system. For example, a method comprises pre-processing received data encoded with a polar code; performing a first decoding of the pre-processed data to obtain output bits; in response to decoding failure of the first decoding, bit-flipping a portion of information bits of the output bits to obtain a first additional frozen bit; and performing a second decoding based on the first additional frozen bit and the pre-processed data. Embodiments of the present disclosure further provide a communication device capable of implementing the above method.

A memory controller system includes error correction circuitry and erasure decoder circuitry. A retry flow is triggered when the memory controller's error checking and correction (ECC) detects an uncorrectable codeword. Error correction circuitry generates erasure codewords from the codeword with uncorrectable errors. The memory controller computes the syndrome weight of the erasure codewords. For example, the erasure decoder circuitry receives the erasure codewords and computes the syndrome weights. Error correction circuitry orders the erasure codewords based on their corresponding syndrome weights. Then error correction circuitry selects a subset of the codewords, and sends them to erasure decoder circuitry. Erasure decoder circuitry receives the selected codewords and decodes them.

A processing device in a memory system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device determines a syndrome for the sense word using the plurality of parity check equation results, determines whether the syndrome for the sense word satisfies a codeword criterion, and responsive to the syndrome for the sense word not satisfying the codeword criterion, performs an iterative low density parity check (LDPC) correction process, wherein at least one criterion of the iterative LDPC correction process is adjusted after a threshold number of iterations is performed.