The present application concerns an iterative bit-flipping decoding method using symbol or bit reliabilities, which is a variation of GRAND decoding and is denoted by ordered reliability bits GRAND (ORBGRAND). It comprises receiving a plurality of demodulated symbols from a noisy transmission channel; and receiving for the plurality of demodulated symbols, information indicating a ranked order of reliability of at least the most unreliable information contained within the plurality of demodulated symbols. A sequence of putative noise patterns from a most likely pattern of noise affecting the plurality of symbols through one or more successively less likely noise patterns is provided. Responsive to the information contained within the plurality of symbols not corresponding with an element of a code-book comprising a set of valid codewords, a first in the sequence of putative noise patterns is used to invert the most unreliable information of the information contained within the plurality of symbols to obtain a potential codeword, and responsive to the potential codeword not corresponding with an element of the code-book, repeatedly: a next likely noise pattern from the sequence of putative noise patterns is applied to invert a noise effect on the received plurality of demodulated symbols to provide a potential codeword, each successive noise pattern indicating an inversion of information for one or more demodulated symbols for a next more reliable combination of information contained within the plurality of symbols, until the potential codeword corresponds with an element of the code-book.

Methods, systems, and apparatuses for stall mitigation in iterative decoders are described. A codeword is received from a memory device. The codeword is iteratively error corrected based on a first bit flipping criterion. A stall condition in the multiple error correction iterations is detected. In response to the detection, the codeword is error corrected based on a second bit flipping criterion that is different from the first bit flipping criterion.

A device for decoding a generalized concatenated code (GCC) codeword includes: a buffer; and at least one processor configured to: obtain the GCC codeword, calculate a plurality of inner syndromes based on a plurality of frames; calculate a plurality of sets of delta syndromes based on the frames; determine a plurality of outer syndromes based on the sets of delta syndromes; store the inner syndromes and the outer syndromes in a buffer; perform inner decoding on the frames based on the inner syndromes stored in the buffer; update at least one outer syndrome stored in the buffer based on a result of the inner decoding; perform outer decoding on the frames based on the updated at least one outer syndrome; and obtain decoded information bits corresponding to the GCC codeword based on a result of the inner decoding and the result of the outer decoding.

A decoder circuit includes first and second decoders. The first decoder is a first type of decoder configured to receive data encoded with an error correction code and decode and eliminate errors from a first subset of codewords of the data. The second decoder is a second type of decoder configured receive the data encoded with the error correction code and decode and eliminate errors from a second subset of codewords of the data, different from the first subset of the codewords, without attempting to decode and eliminate errors from the first subset of the codewords.

For low complexity error correction, a decoder modifies each reliability metric of an input data stream with a random perturbation value. The reliability metric comprises a weighted sum of a channel measurement for the input data stream and parity check results for the input data stream. In addition, the decoder may generate an output data stream as a function of the reliability metrics.

A decoding method includes: receiving a plurality of subcarrier signals each including encoded data; acquiring a predetermined amount of data from each of the plurality of subcarrier signals; correcting errors in the plurality of subcarrier signals by performing decoding arithmetic processing on the respective predetermined amounts of data acquired from the plurality of subcarrier signals in a time-division manner; and causing the decoding arithmetic processing to be consecutively performed on each of the predetermined amounts of data a predetermined number of times.

This disclosure provides systems, methods and apparatus, including computer storage media, for retransmission of sidelink transmissions using network coding with binned feedback. A transmitting device transmits a transport block and a request for a network coding (NC) encoding device to retransmit the transport block to a plurality of user equipment (UEs). The UEs decode the transport block and report an acknowledgment (ACK) or negative acknowledgment (NACK) on a physical sidelink feedback channel (PSFCH) resource associated with a bin for the UEs. The NC encoding device decodes the PSFCH resource for each bin to determine an ACK or NACK status for each bin, and determines whether to encode the transport block in a NC combination packet. The UEs receive the NC combination packet including an encoding of a subset of transport blocks. The receiving devices transmit an ACK or NACK on a PSFCH resource for a bin for each transport block.

A decoder includes one or more Variable-Node Processors (VNPs) that hold respective variables, and logic circuitry. The logic circuitry is configured to decode a code word of an Error Correction Code (ECC), which is representable by a set of check equations, by performing a sequence of iterations such that each iteration involves processing of at least some of the variables, to hold one or more auxiliary equations derived from the check equations, so that a number of the auxiliary equations is smaller than a number of the check equations, to evaluate the auxiliary equations, during the sequence of iterations, using the variables, and, in response to detecting that the variables satisfy the auxiliary equations, to terminate the sequence of iterations and output the variables as the decoded code word.

Systems and methods for correcting corrupted network packets are provided. An example method includes receiving a network packet via a communication channel. The network packet includes a payload and a Cyclic Redundancy Check (CRC) associated with the payload. The method continues with calculating a reference CRC based on the received payload and determining, based on the reference CRC and the received CRC, whether the network packet is corrupted. Based on the determination that the network packet is corrupted, the method continues with selecting a predetermined number of positions of bits in the payload of the network packet, precalculating a set of additional CRCs, and determining, based on the reference CRC and the set of additional CRCs, a combination of bit flips at the predetermined number of positions. The method also includes modifying the payload according to the combination of bit flips at the predetermined number of positions.

A method and apparatus for decoding quasi-cyclic LDPC codes using a vertical layered iterative message passing algorithm. The algorithm of the method improves the efficiency of the check node update by using one or more additional magnitudes, predicted with predictive magnitude maps, for the computation of messages and update of the check node states. The method allows reducing the computational complexity, as well as the storage requirements, of the processing units in the check node update. Several embodiments for the apparatus are presented, using one or more predictive magnitude maps, targeting significant savings in resource usage and power consumption, while minimizing the impact on the error correction performance loss.