A method and apparatus for decoding in which a first failed decode operation is performed on raw bit values of a FEC block by a LDPC decoder. When the FEC block is determined to be a trapped block an updated LLR map is generated; the updated LLR map and either the raw bit values of the FEC block or a failed-decode-output-block from a previous failed decode operation on the trapped block are provided to the LDPC decoder; a decode operation of the LDPC decoder is performed using the updated LLR map on the bit values of the FEC block or the failed-decode-output-block from the previous failed decode operation; and the generating, the providing and the performing are repeated until the decode operation is successful or until a predetermined number of trapped-block-decoding iterations have been performed. When the decode operation is successful in decoding the FEC block the codeword is output.

Systems and methods which provide parallel processing of multiple message bundles for a codeword undergoing a decoding process are described. Embodiments provide low-latency segmented quasi-cyclic low-density parity-check (QC-LDDC) decoder configurations in which decoding process tasks are allocated to different segments of the low-latency segmented QC-LDPC decoder for processing multiple bundles of messages in parallel. A segmented shifter of a low-latency segmented QC-LDPC decoder implementation may be configured to process multiple bundles of a plurality of edge paths in parallel. Multiple bundles of messages of a same check node cluster (CNC) are processed in parallel. Additionally, multiple bundles of messages of a plurality of CNCs are processed in parallel.

Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low-density parity check (LDPC) codes, for example, using a parity check matrix having full row-orthogonality. An exemplary method for performing low-density parity-check (LDPC) decoding includes receiving soft bits associated to an LDPC codeword and performing LDPC decoding of the soft bits using a parity check matrix, wherein each row of the parity check matrix corresponds to a lifted parity check of a lifted LDPC code, at least two columns of the parity check matrix correspond to punctured variable nodes of the lifted LDPC code, and the parity check matrix has row orthogonality between each pair of consecutive rows that are below a row to which the at least two punctured variable nodes are both connected.

Disclosed are a method and an apparatus for fast decoding a linear code based on soft decision. The method may comprise sorting received signals in a magnitude order to obtain sorted signals; obtaining hard decision signals by performing hard decision on the sorted signals; obtaining upper signals corresponding to MRBs from the hard decision signals; obtaining a permuted and corrected codeword candidate using the upper signals and an error vector according to a current order; calculating a cost for the current order using a cost function; determining the permuted and corrected codeword candidate as a permuted and corrected codeword according to a result of comparing the calculated cost with a minimum cost; and determining a predefined speeding condition.

A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.

For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.

For a non-volatile memory that uses hard bit and a soft bit data in error correction operations, architectures are introduced for the compression of the soft bit data to reduce the amount of data transferred over the memory's input-output interface. For a memory device with multiple planes of memory cells, the internal global data bus is segmented and a data compression circuit associated with each segment. This allows soft bit data from a cache buffer of a plane using one segment to transfer data between the cache buffer and the associated compression circuit concurrently with transferring data from a cache buffer of another plane using another segment, either for compression or transfer to the input-output interface.

A memory system includes an encoder and a decoder. The encoder is configured to generate multi-dimensionally-coded data to be written into the non-volatile memory. Data bits of the multi-dimensionally-coded data are grouped into first and second dimensional codes with respect to first and second dimensions, respectively. The decoder is configured to, with respect to each of the first and second dimensional codes included in read multi-dimensionally-coded data, generate a syndrome value of the dimensional code, generate low-reliability location information, generate a soft-input value based on the syndrome value and the low-reliability location information, decode the dimensional code through correction of the dimensional code using the soft-input value, and store modification information indicating a bit of the dimensional code corrected through the correction and reliability information indicating reliability of the correction. The decoder generates the soft-input value also based on the modification information and the reliability information in the memory.

Methods and systems for decoding raw data may include determining a sequence of a plurality of read-level voltages based on previous decoding data and executing a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read-level voltages. Decoded data is returned from the multi-stage decoding operation upon completion of the multi-stage decoding operation and the previous decoding data is updated based on results of the multi-stage decoding operation.

Embodiments of the invention provide a variable node processing unit for a non-binary error correcting code decoder, the variable node processing unit being configured to receive one check node message and intrinsic reliability metrics, and to generate one variable node message from auxiliary components derived from said one check node message and intrinsic reliability metrics, the intrinsic reliability metrics being derived from a received signal, an auxiliary component comprising an auxiliary symbol and an auxiliary reliability metrics associated with said auxiliary symbol, wherein the variable node processing unit comprises: a sorting and redundancy elimination unit configured to process iteratively the auxiliary components and to determine components of the variable node message by iteratively sorting the auxiliary components according to a given order of the auxiliary reliability metrics and keeping a predefined number of auxiliary components comprising the auxiliary symbols that are the most reliable and all different from one another.