The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes. In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 11/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.

A transmitter is provided. The transmitter includes: a low density parity check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits; a repeater configured to select at least a part of bits constituting the LDPC codeword and add the selected bits after the input bits; and a puncturer configured to puncture at least a part of the parity bits.

A decoding method of low-density parity-check (LDPC) codes based on partial average residual belief propagation includes the following steps: S1: calculating a size of a cluster π in a protograph based on a code length m and a code rate of a target codeword; S2: pre-computing an edge residual r.sub.c.sub.i.sub..fwdarw.v.sub.j corresponding to each edge from a variable node to a check node in a check matrix H; S3: calculating, based on π, a partial average residual (PAR) value corresponding to each cluster in the check matrix H; S4: sorting m/π clusters in descending order of corresponding PAR values, and updating an edge with a largest edge residual in each cluster; S5: updating edge information m.sub.c.sub.i.sub..fwdarw.v.sub.i from a check node c.sub.i to a variable node v.sub.j, and then updating a log-likelihood ratio (LLR) value L(v.sub.j) of the variable node v.sub.j; and S6: after the updating, making a decoding decision.

In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.

The method includes: reading a memory cell having a encoded information bit, so as to obtain an LLR value of a current memory cell with reference to a pre-established LLR table according to a storage time, a threshold voltage partition and a comprehensive distribution corresponding to the current memory cell during reading; and performing a soft decoding operation on a codeword in the memory cell having the encoded information bit according to the read LLR value of the current memory cell, wherein the comprehensive distribution of the current memory cell is determined according to an influence of a memory cell adjacent to the current memory cell on a distribution of the current memory cell; an input of the pre-established LLR table comprises a storage time, a threshold voltage partition and a comprehensive distribution, and an output of the pre-established LLR table comprises an LLR value.

A method for operating a storage controller includes receiving a first read command, performing a first read of data stored in a nonvolatile memory using a first read level and receiving a first read data, performing first error correction decoding of the first read data to determine whether the first error correction decoding succeeds, determining a second read level using a predetermined method, and determining a first soft decision offset value of the second read level, reading data stored in the nonvolatile memory using the determined second read level and the first soft decision offset value and receiving a first soft decision data, performing second error correction decoding of the first soft decision data to determine whether the second error correction decoding succeeds, and storing the second read level, a first method used to determine the second read level and the first soft decision offset value.

A decoding method of low-density parity-check (LDPC) codes based on partial average residual belief propagation includes the following steps: S1: calculating a size of a cluster π in a protograph based on a code length m and a code rate of a target codeword; S2: pre-computing an edge residual r.sub.c.sub.i.sub..fwdarw.v.sub.j corresponding to each edge from a variable node to a check node in a check matrix H; S3: calculating, based on π, a partial average residual (PAR) value corresponding to each cluster in the check matrix H; S4: sorting m/π clusters in descending order of corresponding PAR values, and updating an edge with a largest edge residual in each cluster; S5: updating edge information m.sub.c.sub..fwdarw.v.sub.i from a check node c.sub.i to a variable node v.sub.j, and then updating a log-likelihood ratio (LLR) value L(v.sub.j) of the variable node v.sub.j; and S6: after the updating, making a decoding decision.

This application discloses example decoding methods, example decoder, and example decoding apparatuses. One example decodine method includes performing soft decision decoding on a first sub-codeword in a plurality of sub-codewords to obtain a hard decision result. It is determined whether to skip a decoding iteration. In response to determining not to skip the decoding iteration, a first turn-off identifier corresponding to the first sub-codeword is set to a first value based on the hard decision result. The first turn-off identifier indicates whether to perform soft decision decoding on the first sub-codeword in a next decoding iteration. The soft decision decoding is not performed on the first sub-codeword in the next decoding iteration when a value indicated by the first turn-off identifier is the first value. The hard decision result is stored.

A processing device in a memory system receives a request to read data from a memory device. In response to receiving the request, the processing device performs an iterative error correction process on the data, wherein at least one iteration after a first iteration in the error correction process uses a criterion that is based at least partially on a previous iteration or partial iteration, and wherein performing the iterative error correction process comprises flipping any bits in the data having an associated number of unsatisfied parity check equations that satisfies a threshold criterion associated with the previous iteration.

A method and apparatus for performing access control of a memory device with aid of aggressor bit information are provided. The method includes: receiving a first host read command from a host device; sending a first read command to the NV memory in order to try reading first data from a first page; sending a second read command to the NV memory to obtain soft-decoding information and performing a first soft-decoding operation according to the soft-decoding information in order to try obtaining the first data from the first soft-decoding operation; reading multiple bits from at least one aggressor page to be the aggressor bit information; converting the soft-decoding information into adjusted soft-decoding information according to the aggressor bit information of the at least one aggressor page; and performing a second soft-decoding operation according to the adjusted soft-decoding information to obtain the first data from the second soft-decoding operation.