Techniques related to a QoS-aware decoder architecture for data storage are described. In an example, QoS specifications include a QOS latency specification indicative of an acceptable latency for completing the processing of a data read command. The decoder may store this QOS latency specification. In operation, the decoder generates a latency measurement indicative of the actual latency for the processing. If a comparison of the latency measurement and QOS latency specification indicates a violation of the QOS latency specification, the decoder can terminate the decoding and generate a decoding failure.

Provided is an optical transmission/reception device including an error correction decoding unit (36) for decoding a received sequence encoded with an LDPC code, in which the error correction decoding unit (36) is configured to perform decoding processing using a parity check matrix (70) of a spatially-coupled LDPC code, which includes a plurality of parity check sub-matrices (71) combined with each other, in which the decoding processing is windowed decoding processing that uses a window (80) over one or more parity check sub-matrices (71), and in which a window size of the window (80) and a decoding iteration count due to throughput and requested correction performance are variable and input from a control circuit (12) connected to the error correction decoding device (36).

An apparatus includes an interface and a decoder. The interface is configured to receive a code word, produced in accordance with an Error Correction Code (ECC) represented by a set of parity check equations. The code word includes a data part and a redundancy part, and contains one or more errors. The decoder is configured to hold a definition of a partial subgroup of the parity check equations that, when satisfied, indicate that the data part is error-free with a likelihood of at least a predefined threshold, to decode the code word by performing an iterative decoding process on the parity check equations, so as to correct the errors, and during the iterative decoding process, to estimate whether the data part is error-free based only on the partial subgroup of the parity check equations, and if the data part is estimated to be error-free, terminate the iterative decoding process.

The present disclosure relates to a pre-5.sup.th-Generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4.sup.th-Generation (4G) communication system, such as long-term evolution (LTE). The disclosure provides decoding of a low-density parity-check (LDPC) code in a wireless communication system, and a decoding method of the LDPC code may include receiving a codeword, performing decoding iterations on the codeword a predefined maximum number of times using a parity check matrix, performing partial decoding using a partial area of the parity check matrix, and determining decoding success or failure of the codeword based a result of the partial decoding.

Provided herein may be an error correction circuit. An error correction circuit for performing error correction decoding based on an iterative decoding scheme using a NB-LDPC code may include a symbol configuration circuit for configuring an initial symbol to be assigned as a variable node value to a variable node, a reliability value initialization circuit for initializing first reliability values of candidate symbols corresponding to the variable node based on the initial symbol assigned to the variable node, and a symbol correction circuit updating the first reliability values of the candidate symbols based on communications received from a check node coupled to the variable node, the candidate symbols having updated first reliability values, respectively, and adjusting the variable node value to one of the candidate symbols based on a comparison with the updated first reliability value of one of the candidate symbols with a first threshold value.

In some embodiments, a bandwidth constrained equalized transport (BCET) communication system comprises a transmitter that transmits a signal, a communication channel that transports the signal, and a receiver that receives the signal. The transmitter can comprise a pulse-shaping filter that intentionally introduces memory into the signal, and an error control code encoder that is a low-density parity-check (LDPC) error control code encoder. The error control encoder comprises code that is optimized based on the intentionally introduced memory into the signal, a code rate, a signal-to-noise ratio, and an equalizer structure in the receiver. In some embodiments, the communication system is bandwidth constrained, and the transmitted signal comprises an information rate that is higher than for an equivalent system without intentional introduction of the memory at the transmitter.

In one implementation, the disclosure provides a system including a detector configured to generate an output of a first log-likelihood ratio for each bit in an input data stream. The system also includes at least one look-up table providing a mapping of the first log-likelihood ratio to a second log-likelihood ratio. The mapping between the first log-likelihood ratio and the second log-likelihood ratio is non-linear. The system also includes a decoder configured to generate an output data stream using the second log-likelihood ratio to generate a value for each bit in the input data stream.

Systems and methods for implementing data protection techniques with symbol-based variable node updates for binary low-density parity-check (LDPC) codes are described. A semiconductor memory (e.g., a NAND flash memory) may read a set of data from a set of memory cells, determine a set of data state probabilities for the set of data based on sensed threshold voltages for the set of memory cells, generate a valid codeword for the set of data using an iterative LDPC decoding with symbol-based variable node updates and the set of data state probabilities, and store the valid codeword within the semiconductor memory or transfer the valid codeword from the semiconductor memory. The iterative LDPC decoding may utilize a message passing algorithm in which outgoing messages from a plurality of multi-variable nodes are generated using incoming messages (e.g., log-likelihood ratios or L-values) from a plurality of check nodes.

Devices and methods for error correction are described. An exemplary error correction decoder includes a mapper configured to generate, based on a first set of read values corresponding to a first codeword, a first set of log likelihood ratio (LLR) values; a first buffer, coupled to the mapper, configured to store the first set of LLR values received from the mapper; and a node processor, coupled to the first buffer, configured to perform a first error correction decoding operation using the first set of LLR values received from the first buffer, wherein a first iteration of the first error correction decoding operation comprises refraining from updating values of one or more variable nodes, and performing a syndrome check using a parity check matrix and sign bits of the first set of LLR values stored in the first buffer.

A method for punctured bit estimation includes receiving a punctured codeword. The method further includes generating a reconstructed codeword using the punctured codeword and at least one punctured bit having a default logic value. The method further includes generating a syndrome vector for the reconstructed codeword. The method further includes determining, using the syndrome vector, a number of unsatisfied parity-checks for the at least one punctured bit. The method further includes determining, for the at least one punctured bit, a bit value using, at least, the number of unsatisfied parity-checks associated with the at least one punctured bit.