A memory controller, for use in a data storage device, is provided. A low-density parity-check (LDPC) decoding procedure performed by the memory controller includes an initial phase, a decoding phase, and an output phase in sequence. The memory controller includes a memory-index control circuit and a decoder. The decoder includes a decoding pipeline to perform the decoding phase of the LDPC decoding procedure. After the data storage device is booted up, the decoder reads a plurality of first codewords from a variable-node memory using a first order via the memory-index control circuit for LDPC decoding. In response to the decoder determining that a specific codeword among the first codewords has decoding failure, the decoder is reset to read a plurality of second codewords from the variable-node memory using a second order via the memory-index control circuit for LDPC decoding. The first order is different from the second order.

An in-between layer partial syndrome stopping (IBL-PS) criterion for a layered LDPC decoder. The IBL-PS syndrome is obtained by applying the parity checks (H.sub.r,r+1) of a couple of a first layer (r) and a second layer (r+1) on the variables after the first layer has been processed and before the second layer is processed by the decoder, the decoding being stopped if said in-between layer syndrome (s.sub.r,r+1) is satisfied for at least a couple of consecutive layers.

A method employed in a low-density parity-check code decoder includes: receiving a specific data portion of a first codeword; calculating a flipping function value of the specific data portion of the first codeword according to the specific data portion by using checking equations of a parity check matrix to calculate checking values of the specific data portion; and determining whether to flip the specific data portion of the first codeword by comparing the flipping function value with a flipping threshold which has been calculated based on a plurality of flipping function values of a plurality of previous data portions earlier than the specific data portion.

A bit determining method, a memory control circuit unit and a memory storage device are provided. The method includes: reading a first storage state of a first memory cell to obtain a first value of a first significant bit; reading the first storage state of the first memory cell to obtain at least one second value of at least one second significant bit; performing a first decoding operation according to the at least one second value to obtain at least one third value of the decoded second significant bit; determining whether the first significant bit is a special bit according to the first storage state and a second storage state corresponding to the at least one third value; and if the first significant bit is the special bit, performing a corresponding decoding operation.

Provided herein may be an error correction circuit for detecting a trapping set and a method of operating the error correction circuit. The error correction circuit may include a syndrome check history manager configured to maintain a history of syndrome checks corresponding to one or more iterations of the iterative decoding scheme, and a trapping set detector configured to compare a trapping set determination policy with the history of syndrome checks to determine whether the history of syndrome checks meets criteria of the trapping set determination policy, while error correction decoding is performed, and determine that a trapping set exists when the history of syndrome checks satisfies the trapping set determination policy, wherein the trapping set determination policy is related to at least one of a change in a syndrome vector, a number of UCNs, and a change in the number of UCNs.

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

A method of decoding a low density parity check (LDPC) code, includes dividing a parity check matrix of the LDPC code, into a plurality of sub blocks. The method further includes, for each of a plurality of decoding iterations, performing a node operation of each of target sub blocks among the plurality of sub blocks, the target sub blocks corresponding to a present decoding iteration among the plurality of decoding iterations, in a decoding schedule, estimating a reliability of each of the target sub blocks, based on a result of the node operation of each of the target sub blocks, and adjusting the decoding schedule, based on the reliability of each of the target sub blocks.

The present disclosure provides a decoding device. The decoding device includes an iteration number computing unit and a recursive decoder. The iteration number computing unit receives multiple packet parameters corresponding to a packet and computes a codeword-number-per-symbol according to packet parameters, in which the packet includes multiple symbols. The iteration number computing unit computes an iteration number according to the codeword-number-per-symbol. The recursive decoder is coupled to the iteration number computing unit, and performs a decoding operation on a codeword within a data field of the packet according to the iteration number.

Systems and methods described herein provides a method for dynamically allocating an iteration number for a decoder. The method includes receiving, at an input buffer, an input signal including at least one data packet. The method further includes calculating a first iteration number for decoding the at least one data packet. The method further includes monitoring at least one of available space of the input buffer and available decoding time for the at least one data packet. The method further includes dynamically adjusting the first iteration number to a second iteration number based on the available space or the available decoding time to continue decoding the at least one data packet.

Apparatuses and methods related to correcting errors can include using fast decoding (FD) decoders and accurate decoding (AD) decoders. Correcting errors can include receiving input data from the memory array, performing a plurality of operations associated with an error detection on the input data, and providing, based on processing the input data, output data, a validation flag, and a plurality of parity bits to a second decoder hosted by a controller coupled to the memory device.