A memory controller performs an error recovery operation. The controller performs a read operation on a select block using a select read level; decodes data associated with the read operation to generate a syndrome value; determines whether to stop, before a maximum number of iterations, the read operation and the decoding at the select read level, using the syndrome value; when it is determined to stop the read operation and the decoding at the select read level, selects a next read level in a sequence of read levels; and uses the next read level for a subsequent read operation.

An encoding and decoding method of low-density parity-check code is disclosed. The method is following steps: a high rate check code is transferred to a check matrix having a protograph. The check matrix is extended to form an extended base matrix and is split to form a split base matrix. The extended base matrix and the split base matrix are respectively calculated to generate their decoding threshold by a protograph extrinsic information transfer chart. The base matrix with the lower decoding threshold is considered as a low rate base matrix. Repeating the above process until a stop condition is satisfied. The last low rate base matrix is expanded to form a parity check matrix. The transmission data is encoded and decoded by the parity check matrix.

A forward error correction decoder and method of decoding a codeword is provided. The decoder comprises a convergence processor for estimating an expectation of codeword convergence. The convergence processor is configured to calculate a first value of a figure of merit; calculate a second value of the figure of merit; combine the second value of the figure of merit and the first value of the figure of merit to produce a progress value; compare the progress value of the decoding to a progress threshold; and increase a maximum number of iterations of the decoder if the progress value is greater than the progress threshold. The maximum number of iterations may be initially set to a low number beneficial for power consumption and raw throughput. Increasing the maximum number of iterations devotes additional resources to a particular codeword and is beneficial for error rate performance.

A method for using a first decoder operating in a hard decision hard decoding mode to generate soft information for a second decoder operating in a hard decision soft decoding mode includes: generating a look-up table (LUT) linking a number of failed check nodes to a log-likelihood ratio (LLR) value; in a first iteration of the first decoder, inputting the number of failed check nodes to the LUT table to generate an LLR value; and outputting the LLR value to the second decoder.

A method for determining when to end a bit flipping algorithm during hard decision soft decoding in a low density parity check (LDPC) decoder includes: selecting a certain number of iterations as a first threshold; when the first threshold is reached, determining a highest variable node codeword for each iteration performed so far; comparing the highest variable node codewords with a second threshold; and when the value of the highest variable node codewords is less than or equal to the second threshold, ending the bit flipping algorithm.

System and methods described herein includes a method for iterative decoding. The method includes instantiating an iterative decoding procedure to decode a codeword. At each iteration of the iterative decoding procedure, the method further includes retrieving information relating to a plurality of current decoding variables at a current iteration, determining a first current decoding variable to be skipped for the current iteration based on the information, and processing a second decoding variable without processing the first decoding variable to update related decoding variables from the plurality of current decoding variables.

Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. The systems and methods include receiving a data set maintained in a memory device, applying at least one iteration of a data decoding algorithm to the data set by a data decoder circuit to yield a decoded output, counting the number of iterations of the data decoding algorithm applied to the data set to yield an iteration count, and recycling the data set to the memory device. The recycling is triggered based at least in part on the iteration count.

A method for decoding low-density parity check data to decode a codeword is disclosed. The method includes: receiving initial estimates representing a codeword from variable nodes; sending the initial estimates to corresponding check nodes; using all initial estimates to calculate a posteriori probability (APP) values and extrinsic information and sending the APP values and the extrinsic information to the variable nodes; monitoring the extrinsic information (branch information?) received at the check nodes; when the extrinsic information begins to converge, activating a syndrome check for the values at the variable nodes; and when the syndrome check equals zero, activating early termination for the decoding process.

A non-volatile memory (NVM) apparatus and an empty page detection method thereof are provided. The NVM apparatus includes a NVM and a controller. The controller reads the content of a memory page of the NVM. The controller performs Low Density Parity Check (LDPC) decoding for at least one codeword of the memory page to obtain a decoded codeword and a check-result vector. The controller determines that the memory page is not an empty page when the LDPC decoding for the codeword is successful. The controller counts an amount of the bits being 1 (or 0) in the check-result vector when the LDPC decoding for the codeword is fail. Based on the amount of the bits being 1 (or 0) in the check-result vector, the controller determines whether the memory page is an empty page.

In an illustrative example, an apparatus includes a controller and a memory that is configured to store a codeword of a convolutional low-density parity-check (CLDPC) code. The codeword has a first size and includes multiple portions that are independently decodable and that have a second size. The controller includes a CLDPC encoder configured to encode the codeword and a CLDPC decoder configured to decode the codeword or a portion of the codeword.