A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an R message from a previous iteration with a P message to produce a Q message. The P sum adder array adds the P message to a difference of an R message from a current iteration and the R message from the previous iteration to produce an updated P message.

A system for decoding data stored in a non-volatile storage device may include processing circuits configured to decode, in a first iteration, each of a plurality of component codes corresponding to the data by performing a first number of enumerations over hypotheses. The processing circuits may be configured to determine, in the first iteration, an extrinsic value output for each of the component codes based on log-likelihood ratios (LLRs) of one or more error bits of a codeword. The processing circuits may be configured to determine a second number of enumerations based on the extrinsic value. The processing circuits may be configured to decode, in a second iteration, each of the plurality of component codes by performing the second number of enumerations over hypotheses.

The present disclosure relates to a method and an apparatus for decoding data packets in communication network. The method comprises receiving one or more data packets related to each of one or more data types; and decoding the one or more data packets using a parity check matrix associated with the corresponding data type, wherein the parity check matrix comprises a plurality of layers, arranged according to a combination of layers which is determined using a reinforcement model.

Systems and methods for implementing data protection techniques with symbol-based variable node updates for binary low-density parity-check (LDPC) codes are described. A semiconductor memory (e.g., a NAND flash memory) may read a set of data from a set of memory cells, determine a set of data state probabilities for the set of data based on sensed threshold voltages for the set of memory cells, generate a valid codeword for the set of data using an iterative LDPC decoding with symbol-based variable node updates and the set of data state probabilities, and store the valid codeword within the semiconductor memory or transfer the valid codeword from the semiconductor memory. The iterative LDPC decoding may utilize a message passing algorithm in which outgoing messages from a plurality of multi-variable nodes are generated using incoming messages (e.g., log-likelihood ratios or L-values) from a plurality of check nodes.

The present technology includes a controller and a memory system including the same. The controller includes a memory interface configured to receive a codeword from a memory device, and an error correction circuit configured to: perform an error correction decoding operation on the codeword received from the memory interface, compare a number of unsatisfied check nodes (UCNs) detected in the error correction decoding operation with a reference number, perform or stop the error correction decoding operation on the codeword according to a result of comparing the number of UCNs and the reference number, and output a retransmission request signal of the codeword to the memory interface in response to the result, wherein the memory interface requests the codeword to the memory device in response to the retransmission request signal.

An iterative decoder, comprises:

N variable nodes (VNs) v.sub.n, n=1 . . . N, configured to receive a LLR I.sub.n defined on a alphabet A.sub.l of q.sub.ch quantization bits, q.sub.ch≥2;

M constraint nodes (CNs) c.sub.m, m=1 . . . M, 2≤M<N;

v.sub.n and c.sub.m exchanging messages along edges of a Tanner graph;

each v.sub.n sending messages m.sub.v.sub.n.sub..fwdarw.c.sub.m, the set of connected constraint nodes being noted V.sub.(vn), and V.sub.(vn)\{cm} being V.sub.(vn) except c.sub.m, and,

each c.sub.m sending messages m.sub.c.sub.m.sub..fwdarw.v.sub.n to v.sub.n;

the LLR I.sub.n and the messages m.sub.v.sub.n.sub..fwdarw.c.sub.m and m.sub.c.sub.m.sub..fwdarw.v.sub.n are coded; and

each variable node v.sub.n, for each iteration l, compute:

sign-preserving factors:

[00001]$=\xi \times \mathrm{sign}\left(I_n\right)+{.Math.}_{c\in V\left(v_n\right)\backslash \left\{c_m\right\}}\mathrm{sign}\left(\right)$

where ξis a positive or a null integer;

[00002]$=I_n+\frac{1}{2}\times +{.Math.}_{c\in V\left(v_n\right)\backslash \left\{c_m\right\}}\left(\right)$

and

A method of soft decoding received signals. The method comprising defining quantisation intervals for a signal value range, determining a number of bits in each quantisation interval that are connected to unsatisfied constraints, providing, the number of bits in each quantisation interval that are connected to unsatisfied constraints, as an input to a trained model, wherein the trained model has been trained to cover an operational range of a device for soft decoding of signals, determining, using the trained model, a log likelihood ratio for each quantisation interval, and performing soft decoding using the log likelihood ratios.

A processing device in a memory system receives a request to read data from a memory device. In response to receiving the request, the processing device performs an iterative error correction process on the data, wherein at least one iteration after a first iteration in the error correction process uses a criterion that is based at least partially on a previous iteration or partial iteration, and wherein performing the iterative error correction process comprises flipping any bits in the data having an associated number of unsatisfied parity check equations that satisfies a threshold criterion associated with the previous iteration.

The present disclosure relates to a pre-5.sup.th-Generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4.sup.th-Generation (4G) communication system, such as long-term evolution (LTE). The disclosure provides decoding of a low-density parity-check (LDPC) code in a wireless communication system, and a decoding method of the LDPC code may include receiving a codeword, performing decoding iterations on the codeword a predefined maximum number of times using a parity check matrix, performing partial decoding using a partial area of the parity check matrix, and determining decoding success or failure of the codeword based a result of the partial decoding.

Low-density parity-check (LDPC) encoded data with one or more errors and information associated with an early convergence checkpoint are received. The information associated with the early convergence checkpoint is used to perform LDPC decoding on the LDPC encoded data up to the early convergence checkpoint and generate a decoded codeword where the early convergence checkpoint is prior to a first complete iteration of the LDPC decoding. It is determined whether the LDPC decoding is successful and in the event it is determined that the LDPC decoding is successful, the decoded codeword is output.