Memory controllers, decoders and methods to selectively perform bit-flipping (BF) decoding and min-sum (MS) decoding on codewords of an irregular low-density parity-check (LDPC) code. Bit-flipping (BF) decoding is executed with respect to variable nodes having relatively high column weights. MS decoding is executed with respect to variable nodes having relatively low column weights. A column-weight threshold is used to group the variable nodes into the higher and lower column weight groups. The two decoding techniques exchange results during the overall decoding process.

A decoder performs: computing (S501) a value (i,j) of a performance-improvement metric for each kernel K.sub.i,j; and sorting (S502) the kernels in a list in decreasing order of the values (i,j). The decoder then performs a beliefs propagation iterative process as follows: updating (S503) output beliefs for the W top kernels of the list , and propagating said output beliefs as input beliefs of the neighbour kernels of said W top kernels; updating (S504) output beliefs for each neighbour kernel of said W top kernels following update of their input beliefs, and re-computing (S505) the performance-improvement metric value (i,j) for each said neighbour kernel; setting (S505) the performance-improvement metric for said W top kernels to a null value; and re-ordering (S506) the kernels in the list . Then, the decoder repeats the beliefs propagation iterative process until a stop condition is met.

Devices, systems and methods for improving decoding operations of a decoder are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code, the LDPC code having an associated parity matrix comprising N columns, wherein each of at least B columns of the parity matrix has a column weight that exceeds a predetermined column weight, processing the N columns based on a message passing algorithm, and determining, based on the processing, a candidate version of the transmitted codeword, wherein the processing for each of the N columns comprises performing a read operation, a variable node update (VNU) operation, and a check node update (CNU) operation on the first set and the second set, the read operation and the CNU operation on each of the at least B columns spanning two or more time-steps.

An error correcting code (ECC) decoder for a non-volatile memory device is configured to decode data stored by the non-volatile memory device using a parity check matrix with columns of different column weights. The ECC decoder is further configured to artificially slow processing of one or more of the columns of the parity check matrix in response to column weights for the one or more columns satisfying a threshold.

An iterative decoder, comprises:

N variable nodes (VNs) v.sub.n, n=1 . . . N, configured to receive a LLR I.sub.n defined on a alphabet A.sub.l of q.sub.ch quantization bits, q.sub.ch≥2;

M constraint nodes (CNs) c.sub.m, m=1 . . . M, 2≤M<N;

v.sub.n and c.sub.m exchanging messages along edges of a Tanner graph;

each v.sub.n sending messages m.sub.v.sub.n.sub..fwdarw.c.sub.m, the set of connected constraint nodes being noted V.sub.(vn), and V.sub.(vn)\{cm} being V.sub.(vn) except c.sub.m, and,

each c.sub.m sending messages m.sub.c.sub.m.sub..fwdarw.v.sub.n to v.sub.n;

the LLR I.sub.n and the messages m.sub.v.sub.n.sub..fwdarw.c.sub.m and m.sub.c.sub.m.sub..fwdarw.v.sub.n are coded; and

each variable node v.sub.n, for each iteration l, compute:

sign-preserving factors:

[00001]$=\xi \times \mathrm{sign}\left(I_n\right)+{.Math.}_{c\in V\left(v_n\right)\backslash \left\{c_m\right\}}\mathrm{sign}\left(\right)$

where ξis a positive or a null integer;

[00002]$=I_n+\frac{1}{2}\times +{.Math.}_{c\in V\left(v_n\right)\backslash \left\{c_m\right\}}\left(\right)$

and

An error correction circuit includes a memory that stores at least one decoding parameter, a low density parity check (LDPC) decoder that includes a first variable node storing one bit of the data, receives the at least one decoding parameter from the memory, decides a degree of the first variable node based on the at least one decoding parameter, and decides a decoding rule necessary for decoding of the one bit based on the degree of the first variable node, and an adaptive decoding controller that outputs corrected data based on a decoding result of the LDPC decoder.

Examples relate to a decoding apparatus, a decoding device, a decoding method, a decoding computer program, and a communication device, a memory device and a storage device comprising such a decoding apparatus or decoding method. A decoding apparatus for performing iterative decoding on a codeword comprises processing circuitry comprising a plurality of processing units, and control circuitry configured to control the iterative decoding of the codeword. The iterative decoding is based on a parity-check matrix. The matrix is sub-divided into two or more partitions. The control circuitry is configured to operate in a first mode of operation to process a codeword having a first length, and to operate in a second mode of operation to process a codeword having a second length. The control circuitry is configured to multiplex the utilization of the plurality of processing units across the two or more partitions of the matrix at least in the second mode of operation.

Examples relate to apparatuses, devices, methods, and computer programs for generating and employing LDPC (low-density parity-check code) matrices, and to communication devices, memory devices or storage devices comprising such apparatuses or devices. An apparatus for generating an LDPC matrix comprises processing circuitry. The processing circuitry is configured to generate the LDPC matrix using a generator algorithm. The LDPC matrix is generated for codewords with one or more punctured or erased bits. The LDPC matrix is generated observing one or more constraints. For example, the one or more constraints may comprise one or more of the following: a) for each column corresponding to a punctured or erased bit, the LDPC matrix comprises a row comprising a 1 in the column and a 0 in the other columns corresponding to a punctured or erased bit, b) in a row for a given check node, at most two is are present in columns corresponding to punctured or erased bits, and c) each column corresponding to a punctured or erased bit has a column weight of at least 7 and at most 35.

An error correction circuit includes a memory that stores at least one decoding parameter, a low density parity check (LDPC) decoder that includes a first variable node storing one bit of the data, receives the at least one decoding parameter from the memory, decides a degree of the first variable node based on the at least one decoding parameter, and decides a decoding rule necessary for decoding of the one bit based on the degree of the first variable node, and an adaptive decoding controller that outputs corrected data based on a decoding result of the LDPC decoder.

Methods, systems, and devices for wireless communications are described. A wireless communication system may support techniques for correlation-based hardware sequences for layered decoding. In some cases, a user equipment (UE) may partition layers of a submatrix associated with a parity check decoding procedure into a first set of layers and a second set of layers. The UE may sort each set of layers into a respective set of layer orders (e.g., a first set of layer orders and a second set of layer orders) based on an associated set of correlation values. The UE may combine the first set of layer orders and the second set of layer orders to obtain a set of combined layer orders and may select a decoding schedule from a set of decoding schedules used for decoding each of the combined layer orders based on respective schedule lengths for the set of decoding schedules.