This application provides a data processing method, a data processing apparatus, and a communications device. The data processing method includes: coding a first bit sequence, to obtain a second bit sequence, where the first bit sequence includes a first information bit and a first padding bit, and the second bit sequence includes a second information bit and a redundant bit; and storing the second bit sequence in a circular buffer.

A data transmitting method using an LDPC code as an error correction code is provided. The method includes providing a parity check matrix of LDPC code, wherein the size of the parity check matrix is (m1+m2)×(n1+n2); in a sending side, encoding an input data of K bits with a encoder to generate a first block code of (n1+n2) bits, according to the parity check matrix; through a transmitting channel, sending n1 bits of the first block code from the sending side to a receiving side, wherein n2 bits of the first block code are not transmitted; and receiving the n1 bits of the first block code in the receiving side, and using the parity check matrix to perform a decoding algorithm to the received first block code to iterative decodes a second block code of (n1+n2) bits with a decoder. Furthermore, a data decoding method thereof is also provided.

An error correction circuit includes a memory that stores at least one decoding parameter, a low density parity check (LDPC) decoder that includes a first variable node storing one bit of the data, receives the at least one decoding parameter from the memory, decides a degree of the first variable node based on the at least one decoding parameter, and decides a decoding rule necessary for decoding of the one bit based on the degree of the first variable node, and an adaptive decoding controller that outputs corrected data based on a decoding result of the LDPC decoder.

A semiconductor memory system includes: a semiconductor memory device to store a codeword; and a low-density parity check (LDPC) decoder to decode the codeword, based on a parity check matrix, to generate a decoded codeword, wherein the LDPC decoder includes: a selector to select one or more sub-matrices that share the same layer index of the parity check matrix, and select variable nodes corresponding to columns included in the selected one or more sub-matrices based on a threshold value and a number of unsatisfied check nodes (UCNs) connected to the selected variable nodes; a variable node updater to update decision values of variable nodes corresponding to all columns included in the parity check matrix; a syndrome checker to determine whether decoding the codeword has been performed successfully or not; and a check node updater to update a backup syndrome, the threshold value, and a size of a processing unit.

A flash memory controller is configured to decode a codeword. During the decoding process, the flash memory can check the decoding status of each codeword segment in the codeword and skip the decoding of a codeword segment whose decoding status is passed, thereby saving time decoding and also improving decoding efficiency. Even though only a part of the codeword segments in the codeword have been successfully decoded in the decoding process at the previous time, the flash memory controller can replace the part of the codeword segments in the codeword with the correct results obtained previously, and then decoding the re-formed codeword again. Accordingly, the decoding accuracy can be increased and the burden on the subsequent decoding process or data recovery can be reduced.

Systems and methods of communicating using asymmetric polar codes are provided which overcome the codeword length constraints of systems and methods of communicating that use traditional polar codes. Used herein, asymmetric polar codes refers to a polarizing linear block code of any arbitrary length that is constructed by connecting together constituent polar codes of unequal length. Asymmetric polar codes may be known by other names. In comparison to conventional solutions for variable codeword length, asymmetric polar codes may provide more flexibility, improved performance, and/or reduced complexity of decoding, encoding, or code design. The system and method provide a flexible, universal, and well-defined coding scheme and to provide sound bit-error correction performance and low decoding latency (compared with current length-compatible methods which can be used with current hardware designs). For the most part, the provided embodiments can be implemented with nearly all available current encoding/decoding polar code techniques.

Methods, systems, and devices for wireless communications are described. A wireless communication system may support techniques for correlation-based hardware sequences for layered decoding. In some cases, a user equipment (UE) may partition layers of a submatrix associated with a parity check decoding procedure into a first set of layers and a second set of layers. The UE may sort each set of layers into a respective set of layer orders (e.g., a first set of layer orders and a second set of layer orders) based on an associated set of correlation values. The UE may combine the first set of layer orders and the second set of layer orders to obtain a set of combined layer orders and may select a decoding schedule from a set of decoding schedules used for decoding each of the combined layer orders based on respective schedule lengths for the set of decoding schedules.

Memory controllers, decoders and methods to selectively perform bit-flipping (BF) decoding and min-sum (MS) decoding on codewords of an irregular low-density parity-check (LDPC) code. Bit-flipping (BF) decoding is executed with respect to variable nodes having relatively high column weights. MS decoding is executed with respect to variable nodes having relatively low column weights. A column-weight threshold is used to group the variable nodes into the higher and lower column weight groups. The two decoding techniques exchange results during the overall decoding process.

A decoding method for a low density parity check (LDPC) code includes: updating a first check node, among a plurality of check nodes, by receiving, by the first check node, a bit decision and an associated first reliability value from each of a subset of variable nodes including a first variable node among a plurality of variable nodes, calculating a syndrome value and a second reliability value of the first check node based on the received bit decisions and first reliability values, and outputting the calculated syndrome value and second reliability value of the first check node to a variable node of the plurality of variable nodes but not of the subset of variable nodes; and updating the first variable node by receiving, by the first variable node, a syndrome value and a second reliability value of a second check node among the plurality of check nodes, and updating the first reliability value of the first variable node based on the syndrome value and the second reliability value of the second check node.

A decoding method for low-density parity-check (LDPC) code is provided and is configured to decode a communication protocol, which is pending to be tested. The communication protocol includes a code word, and the code word includes a code rate. The decoding method includes: receiving the code word of the communication protocol, which is pending to be tested; determining a parity-check matrix according to the code rate of the code word and saving the parity-check matrix in a dynamic memory; moving the parity-check matrix from the dynamic memory to a first memory and saving the code word in a second memory; sequentially transmitting the code word from the second memory to a plurality of check node units to calculate according to the parity-check matrix in the first memory; transmitting the code word verified by the check node units back to the second memory.