Methods, systems, and apparatuses detect and mitigate a stall condition in an iterative decoder. A codeword is received from a memory device. One or more of the plurality of bits in the codeword are flipped in each of a plurality of error correction iterations. Each bit is flipped using a first bit flipping criterion that includes comparing a first bit flipping threshold and an energy function of each bit. Responsive to the determining an iteration count threshold is satisfied and a parity violation count threshold is satisfied, one or more of the plurality of bits in the codeword are flipped using a second bit flipping criterion for one or more error correction iterations. The second bit flipping criterion differs from the first bit flipping criterion.

A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into FN/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process.

A low-density parity-check decoder utilizes information about hard errors in a storage medium to identify bit locations to flip log-likelihood ratios while attempting to decode codewords. The decoder iteratively flips and saturates log-likelihood ratios for bits at hard error locations and re-decodes until a valid codeword is produced. The decoder also identifies variable nodes associated with trapping sets for iterative log-likelihood ratio bit flipping.

A data processing system includes a likelihood input operable to receive encoded data, a decoder operable to apply a decoding algorithm to likelihood values for the received encoded data and to yield a decoded output, and a decoder input initialization circuit operable to generate new decoder input values based in part on the likelihood values for the received encoded data after the likelihood values for the received encoded data have failed to converge in the decoder.

A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into FN/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process.

A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into FN/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process.

An apparatus having an interface and a control circuit is disclosed. The interface may be configured to process a plurality of read/write operations to/from a memory. The control circuit may be configured to (i) access information that characterizes a plurality of trapping sets of a low-density parity check code in response to receiving data, (ii) encode the data using the low-density parity check code to generate a codeword and (iii) write the codeword in the memory. The generation of the codeword may include at least one of a shortening and a puncturing of a plurality of bits in the codeword. The plurality of bits may be selected based on the information that characterizes the plurality of trapping sets. The bits selected generally reduce a probability that an error correction of the codeword after the codeword is read from the memory fails due to the plurality of trapping sets.

Post-processing circuitry for LDPC decoding includes check node processor for processing shifted LLR values, a hard decision decoder circuitry for receiving processed LLR information and performing parity checks on the processed LLR information. Post-processing control circuitry controls updating of LLR information in the check node processor. The check node processor, hard decision decoder, and control circuitry cooperate to identify check nodes with unsatisfied parity checks after an iteration cycle, identify neighborhood variable nodes that are connected with unsatisfied check nodes, identify satisfied check nodes which are connected to neighborhood variable nodes, and modify messages from neighborhood variable nodes to satisfied check nodes if needed to introduce perturbations to resolve decoding errors. Neighborhood identification circuitry determines which variable nodes are connected with unsatisfied check nodes, that have failed a parity check, and produces a signal indicating which variable nodes are connected to unsatisfied check nodes.

A low-density parity-check (LDPC) apparatus and a matrix trapping set breaking method are provided. The LDPC apparatus includes a logarithm likelihood ratio (LLR) mapping circuit, a variable node (VN) calculation circuit, an adjustment circuit, a check nodes (CN) calculation circuit and a controller. The LLR mapping circuit converts an original codeword into a LLR vector. The VN calculation circuit calculates original V2C information by using the LLR vector and C2V information. The adjustment circuit adjusts the original V2C information to get adjusted V2C information in accordance with a factor. The CN calculation circuit calculates the C2V information by using the adjusted V2C information, and provides the C2V information to the VN calculation circuit. The controller determines whether to adjust the factor. When LDPC iteration operation falls into matrix trap set, the controller decides to adjust the factor so that the iteration operation breaks away from the matrix trap set.

A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into FN/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process.