A processor of an apparatus establishes a wireless communication link with at least one other apparatus via a transceiver of the apparatus. The processor wirelessly communicates with the other apparatus via the wireless communication link by: selecting a first shift-coefficient table from a plurality of shift-coefficient tables; generating a QC-LDPC code using a base matrix and at least a portion of the first shift-coefficient table; selecting a codebook from a plurality of codebooks embedded in the QC-LDPC code; storing the selected codebook in a memory associated with the processor; encoding data using the selected codebook to generate a plurality of modulation symbols of the data; and controlling the transceiver to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus to transmit the modulation symbols of the data to the other apparatus via the wireless communication link.

A data processing apparatus and method with efficient decoding of an LDPC code under bit interleave processing is disclosed. In one example, a data processing apparatus includes a parallel demapping portion configured to obtain a second data stream by executing in parallel demapping processing corresponding to mapping on a transmission side for a first data stream as an object of processing. The apparatus also includes a bit interleave reverse processing portion configured to obtain a third data stream by executing in parallel bit interleave reverse processing corresponding to bit interleave on the transmission side for the second data stream, and an LDPC decoding portion configured to decode the third data stream which is inputted in parallel with a bit group as a unit. The present disclosure, for example, can be applied to a receiving apparatus for a digital broadcasting.

The application is related to a forward error correction mechanism in an optical coherent communication system (CS) comprising a FEC encoder (FE) and a FEC decoder (FD) on the basis of a low density parity check, LDPC, code. The FEC encoder encodes blocks of client bits into codewords by adding parity bits calculated by applying a FEC code to the client bits. Besides, the FEC decoder decodes each codeword by applying thereto an iterative message-passing algorithm, each iteration of the message-passing algorithm comprising evaluating a parity-check matrix defining the FEC code. At the FEC encoder, the coding rate of the FEC code may be varied by varying the number of client/information bits per codeword and/or the number of parity bits per codeword. At the FEC decoder, the parity-check matrix is evaluated column by column at each iteration of the message-passing algorithm. The decoder may be a belief propagation decoder. The computational complexity of the FEC decoder is advantageously weakly dependent and, in some cases, totally independent of the coding rate.

Provided is a method of scheduling a parity check matrix, the method performed by a low-density parity-check (LDPC) decoder, the method including checking at least one non-zero elemental variable node in the parity check matrix, identifying a first index of a row of the parity check matrix in the at least one non-zero elemental variable node, extracting a column in which the at least one non-zero elemental variable node is positionable from the parity check matrix using the first index, and mapping the at least one non-zero elemental variable node to the extracted column based on an arrangement, and identifying a second index of the column of the parity check matrix through the mapped at least one non-zero elemental variable node.

A pipeline ADC comprising an ADC segment and a digital backend coupled to the ADC segment. In some examples the ADC is configured to receive an analog signal, generate a first partial digital code representing a first sample of the analog signal, and generate a second partial digital code representing a second sample of the analog signal. In some examples the digital backend is configured to receive the first and second partial digital codes from the ADC segment, generate a combined digital code based at least partially on the first and second partial digital codes, determine a gain error of the ADC segment based at least partially on a first correlation of a PRBS with a difference between the first and second partial digital codes, and apply a first correction to the combined digital code based at least partially on the gain error of the ADC segment.

The present technique relates to a transmission apparatus, a transmission method, a reception apparatus, and a reception method that can ensure favorable communication quality in data transmission using an LDPC code. LDPC coding is performed based on a check matrix of an LDPC code with a code length N of 69120 bits and a code rate r of 11/16 or 12/16. The LDPC code includes information bits and parity bits, and the check matrix includes an information matrix corresponding to the information bits and a parity matrix corresponding to the parity bits. The information matrix is represented by a check matrix initial value table. The check matrix initial value table is a table indicating positions of elements of 1 in the information matrix on the basis of 360 columns and is a predetermined table. The present technique can be applied to, for example, data transmission using the LDPC code.

Certain aspects of the present disclosure provide low-density parity-check (LDPC) codes having pairwise orthogonality of adjacent rows, and a new decoder that exploits the pairwise row orthogonality for flexible decoder scheduling without performance loss. An apparatus includes a receiver configured to receive a codeword in accordance with a radio technology across a wireless channel via one or more antenna elements situated proximal the receiver. The apparatus includes at least one processor coupled with a memory and comprising decoder circuitry configured to decode the codeword based on a LDPC code to produce a set of information bits. The LDPC code is stored in the memory and defined by a base matrix having columns in which all adjacent rows are orthogonal in a last portion of the rows.

Processors are arranged in a pipeline structure to operate on multiple layers of data, each layer comprising multiple groups of data. An input to a memory is coupled to an output of the last processor in the pipeline, and the memory's output is coupled to an input of the first processor in the pipeline. Multiplexing and de-multiplexing operations are performed in the pipeline. For each group in each layer, a stored result read from the memory is applied to the first processor in the pipeline structure. A calculated result of the stored result is output at the last processor and stored in the memory. Once processing for the last group of data in a first layer is completed, the corresponding processor is configured to process data in a next layer before the pipeline finishes processing the first layer. The stored result obtained from the next layer comprises a calculated result produced from a layer previous to the first layer.

Systems and methods are provided for performing error recovery using LLRs generated from multi-read operations. A method may comprise selecting a set of decoding factors for a multi-read operation to read a non-volatile storage device multiple times. The set of decoding factors may include an aggregation mode for aggregating read results of multiple reads. The method may further comprise issuing a command to the non-volatile storage device to read user data according to the set of decoding factors, generating a plurality of Log-Likelihood Ratio (LLR) values using a mapping engine from a pre-selected set of LLR value magnitudes based on the set of decoding factors, obtaining an aggregated read result in accordance with the aggregation mode and obtaining an LLR value from the plurality of LLR values using the aggregated read result as an index.

A source device includes a forward error correction encoder circuit to generate error correction protected blocks from video data packets. Each error correction protected block includes data words and error correction words. An encoder circuit encode X-bit words of the error correction protected blocks into Y-bit encoded words for transmission to a sink device over one or more multimedia lanes of a multimedia communication link, where X is smaller than Y.