A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

A storage device includes a storage controller, which is configured to receive a command generated by a first virtual machine, from a host, and a non-volatile memory device, which is configured to store first data for the command. The command includes one of a retain command, which is generated to command the storage controller to retain the first data in the non-volatile memory device, or an erase command, which is generated to command the storage controller to erase the first data from the non-volatile memory device, when access between the first virtual machine and the storage controller at least temporarily interrupted.

Techniques for improving the bit error rate (BER) performance of an error correction system are described. In an example, the error correction system implements generalized low-density parity-check (GLDPC) encoding and decoding. To generate a GLDPC codeword, the error correction system accesses data blocks. Each data block includes one or more bits. The error correction system also generates a first constituent codeword of the GLDPC codeword. The first constituent codeword encodes at least a data block from the data blocks and has a first length and a first error correction capability. The error correction system also generates a second constituent codeword of the GLDPC codeword. The second constituent codeword encodes at least the data block and has a second length and a second error correction capability. The second length is different from the first length. The second error correction capability is different from the first error correction capability.

Techniques for improving the bit error rate (BER) performance of an error correction system are described. In an example, the error correction system implements generalized low-density parity-check (GLDPC) encoding and decoding. To generate a GLDPC codeword, the error correction system accesses data blocks. Each data block includes one or more bits. The error correction system also generates a first constituent codeword of the GLPDC codeword. The first constituent codeword encodes at least a data block from the data blocks and has a first length and a first error correction capability. The error correction system also generates a second constituent codeword of the GLPDC codeword. The second constituent codeword encodes at least the data block and has a second length and a second error correction capability. The second length is different from the first length. The second error correction capability is different from the first error correction capability.

A storage device syndrome-weight-based error correction system includes a syndrome-weight-based error correction subsystem coupled to a storage subsystem in a chassis. The syndrome-weight-based error correction subsystem performs a plurality of respective first error correction hard decoding operations on the storage subsystem that each utilize respective read voltage thresholds and that each generate a respective final codeword candidate having a respective syndrome weight. The syndrome-weight-based error correction subsystem identifies a first syndrome weight of a first final codeword candidate that was generated via the performance of one of the plurality of respective first error correction hard decoding operations that utilized first read voltage thresholds and that is lower than the syndrome weights of the final codeword candidates generated via the performance of the others of the plurality of respective first error correction hard decoding operations, and performs error correction soft decoding operations using the first read voltage thresholds.

A data processing method for use in a data processing device, a decoder, a network device and/or a computer-readable storage medium. The data processing method includes: classifying log likelihood ratio (LLR) elements according to a modulation mode, a preset decoder quantization threshold and a signal-to-noise ratio, to obtain a classification result; extracting feature information of each category in the classification result; calculating to obtain a scale factor according to the feature information of each category; and scaling the LLR elements according to the scale factor.

A storage device syndrome-weight-based error correction system includes a syndrome-weight-based error correction subsystem coupled to a storage subsystem in a chassis. The syndrome-weight-based error correction subsystem performs a plurality of respective first error correction hard decoding operations on the storage subsystem that each utilize respective read voltage thresholds and that each generate a respective final codeword candidate having a respective syndrome weight. The syndrome-weight-based error correction subsystem identifies a first syndrome weight of a first final codeword candidate that was generated via the performance of one of the plurality of respective first error correction hard decoding operations that utilized first read voltage thresholds and that is lower than the syndrome weights of the final codeword candidates generated via the performance of the others of the plurality of respective first error correction hard decoding operations, and performs error correction soft decoding operations using the first read voltage thresholds.

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

Provided is an information reconciliation method in a quantum key distribution system between a transmitter and a receiver, which includes receiving a parity bit from the transmitter through a quantum channel, correcting an error of a receiver quantum key by using the received parity bit, and removing a residual error of the receiver quantum key through an open channel by using a cascade protocol to harmonize the receiver quantum key with a transmitter quantum key, wherein the parity bit is generated at the transmitter by using turbo codes. This method may enhance quantum key generation efficiency.