A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

A memory system includes a memory device and a controller. The memory device is configured to output a codeword. The controller is configured to establish, from the codeword, a plurality of variable nodes and a plurality of check nodes, and schedule a decoding operation to ensure that a number of check-sum updates during one cycle of the decoding operation does not exceed a threshold set to be less than a number of the check nodes, wherein the decoding operation includes iterative operations, and each iterative operation includes plural sub-iterative operations.

A processing device in a memory sub-system determines a syndrome weight for a sense word read from a memory device and determines whether the syndrome weight for the sense word satisfies a threshold criterion. Responsive to the syndrome weight for the sense word satisfying a respective threshold criterion associated with a next iteration of a first decoding operation, bypassing the first decoding operation and initiating a second decoding operation for the sense word, wherein the second decoding operation has a higher error correction capability than the first decoding operation.

The present disclosure relates to low-density parity-check (LDPC) encoding methods and apparatus. One example method includes obtaining k information bits to be sent to a receive end, performing LDPC encoding on the k information bits by using a submatrix of ((nk)/Z+j) rows and (n/Z+j) columns at an upper left corner of a check matrix H based on a first transmission code rate R satisfying R=k/(n+jZ), obtaining a first codeword including the k information bits and (nk+jZ) redundant bits, and sending the first codeword to the receive end.

A processing device in a memory sub-system determines a syndrome weight for a sense word read from a memory device and determines whether the syndrome weight for the sense word satisfies a threshold criterion. Responsive to the syndrome weight for the sense word satisfying a respective threshold criterion associated with a next iteration of a first decoding operation, bypassing the first decoding operation and initiating a second decoding operation for the sense word, wherein the second decoding operation has a higher error correction capability than the first decoding operation.