This invention presents a method and apparatus for vertical layered finite alphabet iterative decoding of low-density parity-check codes (LDPC) which operate on parity check matrices that consist of blocks of sub-matrices. The iterative decoding involves passing messages between variable nodes and check nodes of the Tanner graph that associated with one or more sub-matrices constitute decoding blocks, and the messages belong to a finite alphabet. Various embodiments for the method and apparatus of the invention are presented that can achieve very high throughputs with low hardware resource usage and power.

A method for generating encoded data includes: generating at least one local LDPC matrix and a global LDPC matrix, the global LDPC matrix relating to each of the at least one local LDPC matrix; repeatedly selecting one of the at least one local LDPC matrix as a target local LDPC matrix until a number t of the target local LDPC matrices are selected, where t is a user-defined number that is greater than one; generating a block matrix that includes the target local LDPC matrices; generating a primary LDPC matrix that includes a first primary matrix part relating to the block matrix, and a second primary matrix part relating to the global LDPC matrix; and encoding data based on the primary LDPC matrix.

The present disclosure describes apparatuses and methods for implementing an adaptive low-density parity check (LDPC) decoder. In various aspects, an adaptive LDPC decoder processes a first portion of data using first parameters effective to change a status of the LDPC decoder. The LDPC decoder selects second parameters of the LDPC decoder based on the status of the LDPC decoder. The LDPC decoder then processes a second portion of the data with the LDPC decoder using the second parameters and provides decoded data of the channel based on at least the processing the first portion of the data using the first parameters and the processing of the second portion of the data using the second parameters. By adaptively altering the decoding parameters based the status of the decoder, the adaptive LDPC decoder may decode channel data in fewer decoding iterations or with a higher success rate, thereby improving LDPC decoding performance.

A system and method for detecting and correcting memory errors in CXL components is presented. The method includes receiving, into a decoder, a memory transfer block (MTB), wherein the MTB comprises data and parity information, wherein the MTB is arranged in a first dimension and a second dimension. An error checking and a correction function on the MTB is performed using a binary hamming code logic within the decoder in the first dimension. An error checking and a correction function on the MTB is performed using a non-binary hamming code logic within the decoder in the second dimension. Further, the binary hamming code logic and the non-binary hamming code logic perform the error checking on the MTB simultaneously.

A parity check matrix generator for generating a parity check matrix including non-binary cyclic permutation matrices may include: a first memory configured to store a first weight as location information on a non-binary cyclic permutation matrix within the parity check matrix; a second memory configured to store a second weight as cyclic strength of matrix elements of the non-binary cyclic permutation matrix; a third memory configured to store a third weight used to determine a size of a non-binary matrix element among the matrix elements of the non-binary cyclic permutation matrix; and a matrix generator configured to generate the non-binary cyclic permutation matrix by applying a non-binary value to matrix elements of 1's among matrix elements of a binary cyclic permutation matrix having a size corresponding to the non-binary cyclic permutation matrix and reflecting one or more of the first to third weights into the non-binary value.

At least a method and an apparatus are presented for decoding a signal. For example, a decoder is presented for determining an estimate of an encoded signal. The decoder comprises one or more variable node processing units and one or more check node processing units configured to exchange messages, each message comprising one or more components, a component comprising a symbol and a reliability metric associated with the symbol. The at least one check processing unit is further configured to calculate at two or more elementary check node processors a set of syndromes from at least three permuted messages, a syndrome comprising a binary vector; generate at least one check node message from the set of syndromes depending on the binary vector, and send the at least one check node message to a signal estimation unit.

A method for generating encoded data includes: generating at least one local LDPC matrix and a global LDPC matrix, the global LDPC matrix relating to each of the at least one local LDPC matrix; repeatedly selecting one of the at least one local LDPC matrix as a target local LDPC matrix until a number t of the target local LDPC matrices are selected, where t is a user-defined number that is greater than one; generating a block matrix that includes the target local LDPC matrices; generating a primary LDPC matrix that includes a first primary matrix part relating to the block matrix, and a second primary matrix part relating to the global LDPC matrix; and encoding data based on the primary LDPC matrix.

A method for generating encoded data includes: generating at least one local LDPC matrix and a global LDPC matrix, the global LDPC matrix relating to each of the at least one local LDPC matrix; repeatedly selecting one of the at least one local LDPC matrix as a target local LDPC matrix until a number t of the target local LDPC matrices are selected, where t is a user-defined number that is greater than one; generating a block matrix that includes the target local LDPC matrices; generating a primary LDPC matrix that includes a first primary matrix part relating to the block matrix, and a second primary matrix part relating to the global LDPC matrix; and encoding data based on the primary LDPC matrix.

At least a method and an apparatus are presented for determining a coded modulation scheme, the coded modulation scheme being defined by at least one non-binary error correcting code containing at least one non-binary parity-check equation, a modulation scheme, and a modulation mapping. Two or more candidate modulation mappings and two or more candidate parity-check equations are determined defining the at least one non-binary error correcting code, a candidate set comprising a candidate modulation mapping and at least one candidate parity-check equation providing codeword vectors and being associated with one or more metrics, each metric being evaluated for a number of distinct pairs of codeword vectors having an Euclidean distance of a defined value. One candidate modulation mapping and at least one candidate parity-check equation are selected according to an optimization criterion applied to the one or more metrics.

Disclosed are methods and devices for supporting multiple page lengths with unique error correction coding via Galois field dimension folding. In one embodiment, a method comprises receiving a write instruction, the write instruction including user data; generating extended user data based on the user data, the extended user data including at least one symbol comprising a bit of the user data and a pre-stored bit pattern; generating parity data by encoding the extended user data; generating parity extension data by encoding the bit of the user data; writing a codeword to a page of a non-volatile memory device, the codeword including the parity extension data, the user data, and the parity data.