A memory device includes: a memory device configured to store data bits to be written to the memory device; and a memory controller. The memory controller includes: a first level error correction code (ECC) circuit coupled to the memory device, wherein the first level ECC circuit is configured to generate a first plurality of first level check bits corresponding to the data bits based on a first error detection scheme; and a second level ECC circuit coupled to the memory device, wherein the second level ECC circuit is configured to generate a second plurality of second level check bits corresponding to both the data bits and the first plurality of first level check bits based on a first error correction scheme.

Methods and devices are disclosed for encoding source words and decoding codewords with LDPC matrices, comprising: receiving a 1×K source word row vector ū; and generating a 1×N codeword vector c=ū.Math.G, wherein G is a K×N generator matrix derived from a parity check matrix H.sub.l; and wherein H.sub.l is derived from a base parity check matrix H by summing different rows in the base parity check matrix H to obtain an intermediate parity check matrix, and applying a lifting matrix to the intermediate base parity check matrix to obtain H.sub.l.

Embodiments of this application disclose provides a low density parity check (LDPC) channel encoding method for use in a wireless communications system. A communication device encodes an input bit sequence by using a LDPC matrix, to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. Embodiments of the application provide eight particular designs of the base matrix. The encoding method provided in the embodiments of the application can be used in various communications systems including the fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths.

In a multi-antenna communication system using LDPC codes, a simple method is used to effectively improve the received quality by performing a retransmittal of less data without restricting applicable LDPC codes. In a case of a non-retransmittal, a multi-antenna transmitting apparatus (100) transmits, from two antennas (114A,114B), LDPC encoded data formed by LDPC encoding blocks (102A,102B). In a case of a retransmittal, the multi-antenna transmitting apparatus (100) uses a transmission method, in which the diversity gain is higher than in the previous transmission, to transmit only a part of the LDPC encoded data as previously transmitted. For example, the only the part of the LDPC encoded data to be re-transmitted is transmitted from the single antenna (114A).

The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes.

In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 13/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.

Systems and methods for data transport, including encoding streams of input data using generalized low-density parity check (GLDPC) encoders, the one or more GLDPC encoders being configured to generate GLDPC coded data streams using a plurality of component local codes to improve error correction strength, employ single-parity checks and two or more local block codes during generation of the GLDPC codes, and enable continuous tuning of code rate using the generated GLDPC codes. Signals may be generated using mappers, the mappers configured to assign bits of signals to signal constellations and to associate the bits of the signals with signal constellation points. The signal may be modulated using an I/Q or 4-D modulator composed of one polarization beam splitter, two I/Q modulators, and one polarization beam combiner. The modulated signals are multiplexed using a mode-multiplexer, transmitted over a transmission medium, and the signals are received and decoded using GLDPC decoders.

Disclosed herein is an encoder for encoding digital data, said encoder comprising one or more component encoders, one or more interconnections between component encoders, one or more inputs and one or more outputs. The encoder is configured to carry out the following steps:—combining internal input bits received via an interconnection and external input bits received via a corresponding input, to assemble a local information word,—encoding the local information word such as to generate a local code word,—outputting a reduced local code word and handing the same reduced local code word over to said interconnect for forwarding said same reduced local code word via said interconnect to another component encoder or to itself, wherein said encoder is configured to forward on each interconnect the bits of the reduced local code in parallel but with delays that are mutually different for at least a subset of the reduced local code word bits.

A circuit, including an embedded parity matrix generator configured to generate a parity matrix for a data word of any data width; an encoder configured to add a redundancy word to the data word based on the parity matrix; a sub-circuit coupled to the encoder, and configured to receive the data word and the redundancy word from the encoder; and a decoder coupled to the sub-circuit, and configured to receive the data word and the redundancy word from the sub-circuit, and to detect any errors in the data word based on the parity matrix.

A method and apparatus for determining the sector size and concomitant host metadata size to determine the difference between total size of the data block to be stored, and using the difference for parity data. This allows an increase in parity bits available for smaller sector sizes and/or data with smaller host metadata sizes. Because the amount of space available for additional parity bits is known, data with lower numbers of parity bits may be assigned to higher quality portions a memory array written with longer programming trim times, and/or written to memory dies with good redundant columns, further increasing performance and reliability.

Techniques are described for joint encoding and decoding of information symbols. In one embodiment, a method for joint encoding includes, in part, obtaining a sequence of information symbols, generating a plurality of cyclic codewords each corresponding to a portion of the sequence of information symbols, jointly encoding the plurality of cyclic codewords to generate at least one combined codeword, and providing the combined codeword to a device. The at least one combined codeword may be generated through Galois Fourier Transform (GFT). In one embodiment, a method for joint decoding includes, in part, obtaining a sequence of encoded symbols, wherein the sequence of encoded symbols is generated through GFT, jointly decoding the sequence of encoded symbols using an iterative soft decision decoding algorithm to generate a decoded sequence, transforming the decoded sequence to generate a plurality of cyclic codewords, and decoding the plurality of cyclic codewords to generate a plurality of decoded information symbols.