A memory system includes a memory controller. The memory controller executes first calculation of obtaining a first degree to k-th degree error locator polynomials (1≤k<t) by using a syndrome, determines whether error locations can be calculated by the error locator polynomials up to the k-th degree, obtains an initial value of a parameter to be used for second calculation of obtaining error locator polynomials up to t-th degree when it is determined that the error locations cannot be calculated, executes the second calculation using the initial value, calculates the error locations by using an error locator polynomial determined to be able to calculate the error locations among the first degree to k-th degree error locator polynomials or by using error locator polynomials obtained in the second calculation, and corrects errors in the calculated error locations.

A method includes, storing a set of valid codewords including: a first valid functional codeword representing a functional timeout state of a second controller; a first valid fault codeword representing a fault timeout state of the second controller and characterized by a minimum hamming distance from the first valid functional codeword; a second valid functional codeword representing a functional state of a system; and a second valid fault codeword representing a fault state of the system; in response to detecting receipt of a safety message from the second controller within a predefined time quantum, storing the first valid functional codeword in a first memory; in response to detecting a match between contents of the first memory and the first valid functional codeword, outputting the second valid functional codeword; in response to detecting a mismatch between contents of the first memory and every codeword in the first set of valid codewords, outputting the second valid fault codeword.

Codewords of an error correcting code can be received. The codewords can be separated into multiple segments. The segments of the codewords can be distributed in an error correcting layout across a plurality of dies where at least a portion of the error correcting layout constitutes a Latin Square (LS) layout.

An error correction code (ECC) decoder includes a syndrome calculation block and a path controller. The syndrome calculation block is configured to perform a syndrome calculation for generating a syndrome from a codeword. The path controller is configured to output data transmitted through first to third paths. The first path is a path for transmitting the codeword to the path controller when no error is detected. The second path includes a single-error decoding logic circuit, and the single-error decoding logic circuit corrects a single error of the codeword to transmit the corrected codeword to the path controller through the second path. The third path includes a multi-error decoding logic circuit, and the multi-error decoding logic circuit corrects at least two errors of the codeword to transmit the corrected codeword to the path controller.

A system comprises a forward error correction decoder comprising syndrome computation circuitry, key-equation solver circuitry, and search and evaluator circuitry. The syndrome computation circuitry may comprise a plurality of syndrome compute units connected in parallel. The syndrome computation circuitry may be dynamically configurable to vary a quantity of the syndrome compute units used for processing of a codeword based on conditions of a channel over which the codeword was received. The syndrome computation circuitry may be operable to use a first quantity of the syndrome compute units for processing of a first codeword received over the channel when the channel is characterized by a first bit error rate and a second quantity of the syndrome compute units for processing of a second codeword received over the channel when the channel is characterized by a second bit error rate.

Provided are an apparatus, memory device, and method to determine error location polynomial coefficients to provide to bit correction logic instances to decode bits of a codeword. A memory controller for a memory includes coefficient generating logic to receive as input a plurality of syndrome values to generate a plurality of coefficients for an error locator polynomial. A plurality of instances of bit correction logic, one instance for each bit of bits to correct in a codeword for a block in the memory array to decode. Each instance of bit correction logic is to receive as input the coefficients for the error locator polynomial and elements for the bit to correct from a decoder alphabet to determine whether to correct the bit and output as a decoded bit the bit or a corrected bit to include in a decoded codeword.

An error correction code (ECC) decoder includes a syndrome calculation block and a path controller. The syndrome calculation block is configured to perform a syndrome calculation for generating a syndrome from a codeword. The path controller is configured to output data transmitted through first to third paths. The first path is a path for transmitting the codeword to the path controller when no error is detected. The second path includes a single-error decoding logic circuit, and the single-error decoding logic circuit corrects a single error of the codeword to transmit the corrected codeword to the path controller through the second path. The third path includes a multi-error decoding logic circuit, and the multi-error decoding logic circuit corrects at least two errors of the codeword to transmit the corrected codeword to the path controller.

An apparatus for generating encoded data includes processing circuitry configured to encode data using a Mojette transform (MT) based on generating encoded representations of data blocks. Generating the encoded representations of data blocks includes reading data in the form of a data block formatted according to specified settings to comprise rows and columns, creating a set of projections, and outputting the created set of projections to enable storage of the data in the form of the set of projections. The apparatus then transmits the encoded data over a network to another device. Additionally, creating the set of projections includes applying the Mojette transform on the data block, and creating a first number of projections based on mapping each row of the data block to a corresponding projection, wherein the first number of projections carries the same information as a corresponding row.

An H.sub.C of a code B is first transformed into an H.sup.B. A parity bit of the code B is obtained by performing an operation on the H.sup.B and an information bit of the code B. The parity bit is used to perform RS coding on a code A, to obtain a parity bit of the code A. A check code of a GEL code is obtained by performing an operation on the parity bits of the code B and the code A. Finally, a single bit parity check bit is added. The code A is defined in a finite field GF (2.sup.l1), the code B is defined in a finite field GF (2.sup.l2), and l.sub.1 and l.sub.2 are positive integers. A success rate of decoding the code A in the first row can be improved using this method.

A method for decoding an error correction code and an associated decoding circuit are provided, where the method includes the steps of: calculating a set of error syndromes of the error correction code, where the error correction code is a t-error correcting code and has capability of correcting t errors, and a number s of the set of error syndromes is smaller than t; sequentially determining a set of coefficients within a plurality of coefficients of an error locator polynomial of the error correction code according to at least one portion of error syndromes within the set of error syndromes for building a roughly-estimated error locator polynomial; performing a Chien search to determine a plurality of roots of the roughly-estimated error locator polynomial; and performing at least one check operation to selectively utilize a correction result of the error correction code as a decoding result of the error correction code.